Circuit and method for automatically selecting clock modes

1. An apparatus configured to automatically select a clock mode in response to a state of a clock input pin, comprising:

said clock input pin;

a clock output pin; and

a detection circuit configured to generate an output in response to said state of said clock input pin, wherein said output is generated having a first state when an external timing component is connected between said clock input pin and said clock output pin.

2. The apparatus according to claim 1 , wherein said apparatus selects either an internal or an external-based clock mode based on said clock input pin.

3. The apparatus according to claim 1 , wherein said state of said clock input pin comprises one or more states selected from the group consisting of (i) a state connected to a supply voltage ground, (ii) a state connected to a terminal of said external timing component, and (iii) an unconnected state.

4. The apparatus according to claim 1 , wherein said output is generated having a second state when said clock input pin is (i) connected to a voltage supply ground or (ii) unconnected.

5. The apparatus according to claim 1 , further comprising an amplifier circuit configured to generate a first clock signal in response to said external timing component, wherein said first clock signal is presented at said clock output pin.

6. The apparatus according to claim 5 , wherein said amplifier circuit is disabled in response to a control input.

7. The apparatus according to claim 6 , wherein said output is used as said control input.

8. The apparatus according to claim 1 , wherein said external timing component is selected from the group consisting of crystals and ceramic resonators.

9. The apparatus according to claim 1 , wherein said detection circuit, said clock input pin and said clock output pin are implemented as a single chip.

10. The apparatus according to claim 1 , wherein said detection circuit comprises:

a first inverter having a first threshold;

a second inverter having a second threshold; and

a filter circuit coupling an output of said first inverter to an input of said second inverter.

11. The apparatus according to claim 1 , further comprising an oscillator circuit configured to generate a second clock signal.

12. The apparatus according to claim 11 , wherein said second clock signal is an internal clock signal.

13. A method for automatically selecting a clock mode comprising the steps of:

(A) monitoring a clock input pin;

(B) selecting a first clock mode when said clock input pin is in a first predefined state indicative of said clock input pin being coupled to a clock output pin by an external timing component; and

(C) selecting a second clock mode when said clock input pin is in a second predefined state indicative of said clock input pin not being coupled to said clock output pin by said external timing component.

14. The method according to claim 13 , wherein said first predefined state comprises one or more states selected from the group consisting of an amplitude exceeding a predetermined threshold voltage, a frequency exceeding a predetermined threshold frequency, and a clock signal being present.

15. The method according to claim 13 , wherein said second predefined state comprises one or more states selected from the group consisting of an amplitude below a predetermined threshold voltage, a frequency less than a predetermined threshold frequency, and a clock signal not being present.

16. The method according to claim 13 , wherein step (A) comprises the sub-step of:

(A-1) detecting a voltage supply ground.

17. The method according to claim 13 , wherein step (A) comprises the sub-step of:

(A-1) detecting said external timing component.

18. The method according to claim 13 , wherein step (A) comprises the sub-step of:

(A-1) detecting a voltage characteristic of said clock input pin.

19. The method according to claim 13 , wherein step (C) comprises the sub-step of:

(C-1) disabling one or more components of a clock generator coupled to said clock output pin.

20. The method according to claim 19 , wherein step (C) further comprises the sub-step of:

(C-2) configuring said clock input pin and said clock output pin for one or more alternate functions.

21. An apparatus for automatically selecting a clock mode comprising:

means for monitoring a clock input pin;

means for selecting a first clock mode when said clock input pin is in a first predefined state indicative of said clock input pin being coupled to a clock output pin by an external timing component selected from the group consisting of crystals and ceramic resonators; and

means for selecting a second clock mode when said clock input pin is in a second predefined state indicative of said clock input pin not being coupled to said clock output pin by said external timing component.