Merging of infrastructure within a development environment

1. A method for designing a circuit comprising:

generating netlists for subsystems of infrastructure for the circuit within a first hardware description language development environment;

generating hardware description language for a primary logic component using a graphical design tool, the hardware description language including representations of the subsystems of the infrastructure;

performing an adjust process to reconcile ports for the subsystems, as represented in the hardware description language generated using the graphical design tool, with the generated infrastructure, the adjust process resulting in adjusted hardware description language; and,

generating a design for the circuit by merging the infrastructure and the adjusted hardware description language.

2. The method of claim 1 wherein the circuit is a programmable logic device.

3. The method of claim 1 wherein the primary logic component performs at least one of the following:

digital signal processing algorithms;

mathematical operations associated with at least one of the following:

measurement,

test,

control,

communications.

4. The method of claim 1 wherein the infrastructure performs input/output functions for the primary logic component.

5. A development environment comprising:

a graphical design tool that allows a designer to design a primary logic component of a circuit, the graphical design tool generating modules using a hardware description language to represent the primary logic component of the circuit, the modules including abstract references to infrastructure for the circuit; and,

a build agent that synthesizes the modules into netlists and merges the netlists with a description of the infrastructure for the circuit, netlists for the infrastructure having been generated in a development environment separate from the graphical design tool, the build agent including:

an adjuster that adjusts the modules, including replacing the abstract references to the infrastructure, with actual references utilized within the infrastructure.

6. The development environment of claim 5 wherein the abstract references to the infrastructure include ports of subsystems contained within the infrastructure.

7. The development environment of claim 5 wherein the graphical design tool includes an infrastructure chooser that allows the designer to select sets of infrastructure to include within the circuit.

8. The development environment of claim 5 wherein subsystems of the infrastructure include at least one of the following:

circuitry to provide clocks to digital logic;

circuitry to provide synchronization to digital logic;

an interface to an application specific integrated circuit;

an interface to a microprocessor;

an interface to a microcontroller;

an interface to a digital signal processor;

an interface to a programmable logic device;

an interface to a communications integrated circuit;

an interface to a communications subsystem;

an interface to a bus;

an interface to a memory subsystem;

an interface to an analog-to-digital converter;

an interface to a digital-to-analog converter;

an interface to a transducer;

an interface to a general-purpose input/output subsystem.

9. The development environment of claim 5 wherein the circuit is a programmable logic device.

10. The development environment of claim 5 wherein the primary logic component performs at least one of the following:

digital signal processing algorithms;

mathematical operations associated with at least one of the following:

measurement,

test,

control,

communications.

11. The development environment of claim 5 wherein the infrastructure performs input/output functions for the primary logic component.

12. A development environment comprising:

design means for allowing a designer to design, within a graphical design environment, a primary logic component of a circuit, the design means generating modules using a hardware description language to represent the primary logic component of the circuit, the modules including abstract references to infrastructure for the circuit; and,

merging means for synthesizing the modules into netlists and merging the netlists with a description of the infrastructure for the circuit, netlists for the infrastructure having been generated in a development environment separate from the design means, the merging means including:

adjusting means for adjusting the modules, including replacing the abstract references to the infrastructure, with actual references utilized within the infrastructure.

13. The development environment of claim 12 wherein the abstract references to the infrastructure include ports of subsystems contained within the infrastructure.

14. The development environment of claim 12 wherein the design means includes an infrastructure chooser that allows the designer to select subsystems of infrastructure to include within the circuit.

15. The development environment of claim 12 where subsystems of the infrastructure include at least one of the following:

circuitry to provide clocks to digital logic;

circuitry to provide synchronization to digital logic;

an interface to an application specific integrated circuit;

an interface to a microprocessor;

an interface to a microcontroller;

an interface to a digital signal processor;

an interface to a programmable logic device;

an interface to a communications integrated circuit;

an interface to a communications subsystem;

an interface to a bus;

an interface to a memory subsystem;

an interface to an analog-to-digital converter;

an interface to a digital-to-analog converter;

an interface to a transducer;

an interface to a general-purpose input/output subsystem.

16. The development environment of claim 12 wherein the circuit is a programmable logic device.

17. The development environment of claim 12 wherein the primary logic component performs at least one of the following:

digital signal processing algorithms;

mathematical operations associated with at least one of the following:

measurement,

test,

control,

communications.

18. The development environment of claim 12 wherein the infrastructure performs input/output functions for the primary logic component.

19. The development environment of claim 12 wherein constraints for the infrastructure are also generated in the development environment separate from the design means.

20. The development environment of claim 5 wherein constraints for the infrastructure are also generated in the development environment separate from the graphical design tool.