Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors
View Patent ↗Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact with the array traces to provide extended ESD protection until removal of those shorting elements during normal processing for opening vias for photodiode bottom contact.
1. A method for providing electrostatic discharge protection during fabrication processing of photodiode array panels comprising the steps of:
depositing first trace and pad features in a first metal layer on a glass substrate;
etching to define the trace and pad contours;
depositing a first dielectric layer over the first metal layer;
etching the first dielectric layer to provides first vias through the dielectric layer;
depositing a second metal layer contacting the first metal layer through the first vias providing a shorting bar for contact between the traces during further handling and processing for ESD protection;
depositing a second dielectric layer;
creating a second via surrounding the shorting bar during normal processing for connection of a third metal layer to the second metal layer;
depositing the third metal layer;
masking the third metal for etching;
removing the photoresist around the shorting bar; and,
etching the third metal layer and the shorting bar.
2. A method as defined in claim 1 wherein the second via is about 20 μm×40 μm.
3. A method as defined in claim 1 wherein the shorting bar is sized with a relative width narrow enough to allow the same etching recipe for removal of the third metal layer to perform the etching of the shorting bar.
4. A method as defined in claim 3 wherein the shorting bar width is defined so side etching occurs faster than top etching and the shorting bar is eliminated in its entirety during the etch.
5. A method as defined in claim 4 wherein the shorting bar width is about 5 μm.
6. A method as defined in claim 1 wherein the first dielectric layer is a-Si.
7. A method as defined in claim 1 wherein the second dielectric layer is a SiO2 multilayer.