IP Library Granted Patent US 6,970,036
Granted Patent B2
US 6,970,036 · App. 10/860,011 · Granted Nov 29, 2005

Semiconductor integrated circuit device

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Quick Facts
Patent No.
US 6,970,036
App. No.
10/860,011
Granted
Nov 29, 2005
Kind
B2
Abstract

A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Claims (13)

1. A semiconductor integrated circuit device comprising:

a power control circuit; and

a plurality of first circuits, each of the plurality of first circuits having at least a first state (active) and a second state (standby);

wherein a power consumption of the first circuit in the first state is higher than the power consumption of the first circuit in the second state, and

wherein the power control circuit controls a state of each of the plurality of first circuits, based on the power consumption of the plurality of the first circuits.

2. The semiconductor integrated circuit device according to claim 1 , further comprising:

a second circuit to be privileged to access each of the first circuits;

wherein one of the first circuit is controlled to be in the second state, even when the second circuit has necessity to access the one of the first circuit.

3. The semiconductor integrated circuit device according to claim 1 ,

wherein the second circuit issues a request to the power control circuit and access the one of the first circuit when the power control circuit allow the second circuit to access the one of the first circuits.

4. The semiconductor integrated circuit device according to claim 1 , wherein, when the first circuit is in the second state, no clock is supplied to the first circuit.

5. The semiconductor integrated circuit device according to claim 1 , wherein, when the first circuit is in the second state, no supply voltage is supplied to the first circuit.

6. The semiconductor integrated circuit device according to claim 1 , wherein, when the first circuit is in the second state, leakage current is suppressed.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
MERGER Recorded Jul 7, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024662/0280 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2004
From: MIZUNO, HIROYUKI
To: HITACHI LTD.
Reel/Frame 015434/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2004
From: HITACHI, LTD.
To: RENESAS TECHHOLOGY CORPORATION
Reel/Frame 015434/0157 →