Error detection and correction method and system for memory devices
View Patent ↗A method and a system for the detection and correction of errors in memory systems is disclosed. In one embodiment, a method of error detection in a memory system having a plurality (m>1) of memory devices includes generating check bits for each of a plurality of data sets, dividing each memory device into a plurality (n>1) of segments. The plurality of data sets are interleaved to form a plurality (p>1) of words. Each word includes at least one segment from two or more of the memory devices. Detection and correction may utilize oneor more parallel Reed-Solomon decoder and encoder. The system and method allow for the efficient detection and/or correction of memory device errors and bit errors in one or more memory devices.
1. A memory system, comprising:
m memory devices, each device being divided into n segments, wherein m and n are greater than one, each memory device adapted to include a single bit per storage cell;
at least one encoder adapted to generate check bits for a plurality of data; and
an interleaving module adapted to interleave the plurality of data to form p words, each word including at least one segment from two or more of said memory devices,
wherein the at least one encoder is a parallel Reed-Solomon encoder.
2. The system according to claim 1 , wherein the at least one encoder is adapted to generate check bits for different data.
3. A memory system, comprising:
m memory devices, each device being divided into n segments, wherein m and n are greater than one, each memory device adapted to include a single bit per storage cell;
at least one encoder adapted to generate check bits for a plurality of data, wherein the at least one encoder is adapted to generate check bits for different data;
an interleaving module adapted to interleave the plurality of data to form p words, each word including at least one segment from two or more of said memory devices; and
at least one decoder receiving de-interleaved data from the interleaving module and providing the data as corrected data.
4. The system according to claim 3 , wherein the at least one decoder is a parallel Reed-Solomon decoder.
5. The system according to claim 1 , wherein m=8.
6. The system according to claim 1 , wherein n=2.
7. The system according to claim 6 , wherein p=2.
8. The system according to claim 6 , wherein p>2.
9. A memory system, comprising:
m memory devices, each device being divided into n segments, wherein m and n are greater than one, each memory device adapted to include a single bit per storage cell;
at least one encoder adapted to generate check bits for a plurality of data;
an interleaving module adapted to interleave the plurality of data to form p words, each word including at least one segment from two or more of said memory devices; and
a radiation-mitigating shield adapted to shield components of said memory system.
10. The system according to claim 9 , wherein the at least one encoder is adapted to generate check bits for different data.
11. The system according to claim 9 , wherein m=8.
12. The system according to claim 9 , wherein n=2.
13. The system according to claim 12 , wherein p=2.
14. The system according to claim 12 , wherein p>2.
15. The system according to claim 1 , further comprising at least one decoder receiving de-interleaved data from the interleaving module and providing the data as corrected data.
16. The system according to claim 15 , wherein the at least one decoder is a parallel Reed-Solomon decoder.
17. The system according to claim 1 , further comprising a radiation-mitigating shield adapted to shield components of said memory system.
18. The system according to claim 3 , wherein m=8.
19. The system according to claim 3 , wherein n=2.
20. The system according to claim 19 , wherein p=2.
21. The system according to claim 19 , wherein p>2.
22. The system according to claim 3 , further comprising a radiation-mitigating shield adapted to shield components of said memory system.