Flexible memory interface system for independently processing different portions of an instruction
View Patent ↗A flexible memory interface system includes a control module, instruction memory, a command processing unit, an address processing unit, and a data processing unit. The control module controls storing and retrieving of a command portion, an addressing portion, and data of an instruction to access memory to and from the instruction memory and the command processing unit, the address processing unit, and the data processing unit, respectively. The command processing unit is operably coupled to process a command portion of an instruction to access memory. The address processing unit is operably coupled to process an addressing portion of the instruction to access the memory. The data processing unit is operably coupled to process data conveyance to or from the external memory based on the instruction to access the memory.
1. A method for processing an instruction to access various memories, the method comprises:
processing a command portion of an instruction to access memory to determine whether data is to be written into a memory or read from the memory;
processing, independently of the processing the command portion, an addressing portion of the instruction to access the memory to determine an address location within the memory; and
in response to the instruction to access the memory including data in a data portion, processing, independently of the processing the command portion and the address portion, the data in the data portion for conveyance to the memory based on the instruction to access the memory.
2. The method of claim 1 , wherein the processing the data in the data portion for conveyance to the memory further comprises:
storing the data in the data portion within a buffer for subsequent writing to the memory when the instruction to access the memory is a write instruction.
3. The method of claim 1 further comprises:
writing the data in the data portion to the memory at the address location when the command portion is a write request; and reading the data in the data portion from the address location of the memory when the command portion is a read request.
4. The method of claim 1 further comprises:
controlling storing and retrieving of the command portion, the addressing portion, and the data in the data portion from an instruction memory for the independent processing of the command portion, the address portion, and the data in the data portion for conveyance to the memory.
5. The method of claim 4 further comprises:
utilizing a retrieval sequence of the command portion, the address portion, and the data in the data portion from the instruction memory in accordance with an access protocol of the memory.
6. The method of claim 5 further comprises:
determining size of the command portion, the address portion, and the data in the data portion of the instruction to access the memory based on the access protocol of the memory.
7. The method of claim 5 further comprises:
negotiating with the memory to determine the access protocol of the memory.
8. The method of claim 7 , wherein the determining the access protocol further comprises:
reading an ID field of the memory determine an identity of the type of memory; and
based on the type of memory, determining the access protocol.
9. An apparatus for processing an instruction to access various memories, the apparatus comprises:
processing module; and
memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to:
process a command portion of an instruction to access memory to determine whether data is to be written into a memory or read from the memory;
process, independently of the processing the command portion, an addressing portion of the instruction to access the memory to determine an address location within the memory; and
in response to the instruction to access the memory including data in a data portion, process, independently of the processing the command portion and the address portion, the data in the data portion for conveyance to the memory based on the instruction to access the memory.
10. The apparatus of claim 9 , wherein the memory further stores operational instructions that cause the processing module to process the data in the data portion for conveyance to the memory by:
storing the data in the data portion within a buffer for subsequent writing to the memory when the instruction to access the memory is a write instruction.
11. The apparatus of claim 9 , wherein the memory further stores operational instructions that cause the processing module to:
write the data in the data portion to the memory at the address location when the command portion is a write request; and
read the data from the address location of the memory when the command portion is a read request.
12. The apparatus of claim 9 , wherein the memory further stores operational instructions that cause the processing module to:
determine size of the command portion, the address portion, and the data in the data portion of the instruction to access the memory based on the access protocol of the memory.
13. The apparatus of claim 9 , wherein the memory further stores operational instructions that cause the processing module to:
control storing and retrieving of the command portion, the addressing portion, and the data in the data portion from an instruction memory for the independent processing of the command portion, the address portion, and the data in the data portion for conveyance to the memory.
14. The apparatus of claim 13 , wherein the memory further stores operational instructions that cause the processing module to:
utilize a retrieval sequence of the command portion, the address portion, and the data in the data portion from the instruction memory in accordance with an access protocol of the memory.
15. A flexible memory interface system comprises:
command processing unit operable to process a command portion of an instruction to access memory;
address processing unit operable to process an addressing portion of the instruction to access the memory; and
data processing unit operable to process data in the data portion for conveyance to the memory in response to the instruction to access the memory including the data in a data portion;
wherein the command processing unit, the address processing unit and the data processing unit are configured in parallel to independently process the command portion, the addressing portion, and the data in the data portion for conveyance to the memory respectively.
16. The flexible memory interface system of claim 15 further comprises:
control module; and
instruction memory, wherein the control module is further operable to store and retrieve the command portion, the addressing portion, and the data in the data portion from the instruction memory with the command processing unit, the address processing unit, and the data processing unit, respectively.
17. The flexible memory interface system of claim 16 further comprises:
the instruction memory operable to store a plurality of instructions to access the memory, wherein each instruction of the plurality of instructions to access the memory includes at least a command portion and an address portion, wherein the control module is further operable to, for each of the plurality of instructions to access the memory, store and retrieve the command portion, the addressing portion, and associated data in the data portion of the instruction memory in an asynchronous manner.
18. The flexible memory interface system of claim 17 wherein further the control module is operable to store the command portions of the plurality of instructions to access the memory, to store the address portions of the plurality of instructions to access the memory, and to store the associated data in the data portion of the plurality of instructions to access the memory in an interleaved manner within the instruction memory.
19. The flexible memory interface system of claim 17 wherein further the control module is operable to utilize a retrieval sequence of the command portion, the address portion, and the associated data in the data portion of the instruction memory in accordance with an access protocol of the memory.
20. The flexible memory interface system of claim 16 wherein further the control module is operable to determine a size of the command portion, the address portion, and the data in the data portion of the instruction to access the memory based on access protocol of the memory.
21. The flexible memory interface system of claim 16 , wherein the control module is further operable to:
determine whether the memory is a first type of memory or a second type of memory;
process the instruction using a first access protocol in response to the flexible memory interface being coupled to the first type of memory; and
process the instruction using a second access protocol in response to the flexible memory interface being coupled to the second type of memory.
22. The flexible memory interface system of claim 16 wherein further the control module is operable to negotiate with the memory to determine access protocol of the memory.
23. The flexible memory interface system of claim 22 , wherein further, in determining the access protocol the control module is operable to read an ID field of the memory to determine an identity of the type of memory and based on the type of memory, to determine the access protocol.
24. The flexible memory interface system of claim 15 , wherein further:
the command processing unit includes a command buffer operable to store a plurality of command portions;
the address processing unit includes an address buffer operable to store a plurality of address portions; and
the data processing units includes a data buffer operable to store the data in the data portion for conveyance to the memory.
25. The flexible memory interface system of claim 15 , wherein the flexible memory interface is operable to:
process the instruction using a first access protocol in response to the flexible memory interface being coupled to a first type of memory; and
process the instruction using a second access protocol in response to the flexible memory interface being coupled to a second type of memory.