Device for reproducing received data for radio data communication and a method of adjusting frequency therefor
View Patent ↗A receiver arrangement including a received data reproducing device includes an RF (Radio Frequency) receiver configured to determine the signal strength of a received signal and feed it to a clock frequency determining circuit. Number-of-error information, included in the outputs of a clock phase detector and produced during error detection effected with a sync word, a packet header and a payload of a packet field by field, are also fed to the clock frequency determining circuit. The clock frequency determining circuit designates a subject to deal with the packet and selects single clock frequency information out of clock frequencies determined. The clock frequency information thus selected is input to the clock phase detector.
1. A received data reproducing device comprising:
a measuring circuit for measure a signal strength of a received signal;
an optimum phase detecting circuit for dividing a phase of a frequency particular to the received signal into N, where N is 2 or greater integer, to sample the received signal with a sampling signal multiplied in accordance with N, storing a sampled value for each of divided phases, outpouring optimum clock phase information for the received data derived from error information of each field, which is set in accordance with a communication standard of the received signal, and output error presence/absence information obtained in the event of detection of the error information;
a frequency determining circuit for determining an optimum frequency of the sampling signal on the basis of the signal strength measured, the error presence/absence information output field by field and link information indicative of a station communicating with said received data reproducing device, and feed the optimum frequency information to said optimum phase detecting circuit;
a buffer circuit for taking in the received signal and then adjusting the phase of the received signal with individual clock phase information corrected to read out the received signal;
a sync word detector for executing processing for detecting synchronizing data included in input data, which are fed via a phase sampling/storing circuit for sampling the baseband signal with the sampling signal in accordance with a phase of said baseband signal while sequentially storing resulting sampled data, to thereby output synchronization detection information, checking, during the processing, every packet produced by dividing the input data for errors, and outputting, as the error presence/absence information, number-of-error information relating to synchronization and reflecting a result of checking;
an error confirming circuit arranged in parallel to said sync word detector for comparing data relating to errors and generated when the data are present with, among the input data, data relating to errors to thereby confirm accurate receipt to output optimum phase information derived from error detection, and checking every packet for errors to output number-of-error information reflecting a result of checking as the error presence/absence signal;
a phase counter for cyclically outputting a count, which is output in synchronism with the sampling signal, as optimum clock phase information;
a phase information latch for latching the optimum clock phase information in response to a confirmation signal representative of accurate receipt and fed to said optimum phase detecting circuit field by field, and then outputting the optimum clock phase information; and
a sampling signal generator supplied with N-time information from an outside of said optimum phase detecting circuit as a clock control signal for generating, in accordance with N indicated by the clock control signal, a sampling signal N times as high as the baseband signal in frequency.
2. The device in accordance with claim 1 , wherein said measuring circuit demodulates the received signal transmitted by radio to thereby convert the received signal to a baseband signal.
3. The device in accordance with claim 2 , wherein said frequency determining circuit comprises:
a plurality frequency deciders each being assigned to a particular station to communicate for calculating a frequency of the sampling signal on the basis of the signal strength and the number-of-error information and determining whether or not the frequency calculated is optimum; and
an output selector for selecting frequency information, which has the frequency determined to be optimum, in accordance with the link information and outputting the frequency information to said optimum phase detecting circuit.
4. The device in accordance with claim 3 , wherein said plurality frequency deciders each update and store, in accordance with characteristics of the received signal, a program used to calculate the frequency of the sampling signal.
5. The device in accordance with claim 4 , further comprising:
an error confirming circuit arranged in parallel to said sync word detector for comparing data relating to errors and generated when the data are present with, among the input data, data relating to errors to thereby confirm accurate receipt to output optimum phase information derived from error detection, and checking every packet for errors to thereby output number-of-error information reflecting a result of checking as the error presence/absence signal;
wherein said optimum phase detecting circuit is connected to generate, as an optimum clock, a frequency adjusted in accordance with the optimum frequency information determined by said sampling signal generator and a switch timing signal fed from an outside of said optimum phase detecting circuit, and feed the optimum clock to said sync word detector and said error confirming circuit, and
wherein a timing controller is arranged outside of said optimum phase detecting circuit for generating the switch timing signal used to take in the clock frequency information.
6. The device in accordance with claim 5 , wherein said switch timing signal is generated at a boundary between items included in the baseband signal, which is divided by a preselected cycle division, and subjects of detection of the optimum phase information.
7. The device in accordance with claim 3 , further comprising:
an error confirming circuit arranged in parallel to said sync word detector and for comparing data relating to errors and generated when the data are present with, among the input data, data relating to errors to thereby confirm accurate receipt to output optimum phase information derived from error detection, and checking every packet for errors to output number-of-error information reflecting a result of checking as the error presence/absence signal;
wherein said optimum phase detecting circuit is connected to generate, as an optimum clock, a frequency adjusted in accordance with the optimum frequency information determined by said sampling signal generator and a switch timing signal fed from an outside of said optimum phase detecting circuit, and feed the optimum clock to said sync word detector and said error confirming circuit, and
wherein a timing controller is arranged outside of said optimum phase detecting circuit for generating the switch timing signal used to take in the clock frequency information.
8. The device in accordance with claim 7 , wherein said switch timing signal is generated at a boundary between items included in the baseband signal, which is divided by a preselected cycle division, and subjects of detection of the optimum phase information.
9. The device in accordance with claim 2 , further comprising:
an error confirming circuit arranged in parallel to said sync word detector for comparing data relating to errors and generated when the data are present with, among the input data, data relating to errors to thereby confirm accurate receipt to output optimum phase information derived from error detection, and checking every packet for errors to output number-of error information reflecting a result of checking as the error presence/absence signal;
wherein said optimum phase detecting circuit is connected to generate, as an optimum clock, a frequency adjusted in accordance with the optimum frequency information determined by said sampling signal generator and a switch timing signal fed from an outside of said optimum phase detecting circuit, and feed the optimum clock to said sync word detector and said error confirming circuit, and
wherein a timing controller is arranged outside of said optimum phase detecting circuit for generating the switch timing signal used to take in the clock frequency information.
10. The device in accordance with claim 9 , wherein said switch tuning signal is generated at a boundary between items included in the baseband signal, which is divided by a preselected cycle division, and subjects of detection of the optimum phase information.
11. The device in accordance with claim 1 , wherein said frequency determining circuit comprises:
a plurality frequency deciders each being assigned to a particular station to communicate for calculating a frequency of the sampling signal on the basis of the signal strength and the number-of-error information and determining whether or not the frequency calculated is optimum; and
an output selector for selecting frequency information, which has the frequency determined to be optimum, in accordance with the link information and output the frequency information to said optimum phase detecting circuit.
12. The device in accordance with claim 11 , wherein said plurality frequency deciders each update and store, in accordance with characteristics of the received signal, a program used to calculate the frequency of the sampling signal.
13. The device in accordance with claim 1 , further comprising:
an error confirming circuit arranged in parallel to said sync word detector for comparing data relating to errors and generated when the data are present with, among the input data, data relating to errors to thereby confirm accurate receipt to output optimum phase information derived from error detection, and checking every packet for errors to output number-of-error information reflecting a result of checking as the error presence/absence signal;
wherein said optimum phase detecting circuit is connected to generate, as an optimum clock, a frequency adjusted in accordance with the optimum frequency information determined by said sampling signal generator and a switch timing signal fed from an outside of said optimum phase detecting circuit, and feed the optimum clock to said sync word detector and said error confirming circuit, and
wherein a timing controller is arranged outside of said optimum phase detecting circuit for generating the switch timing signal used to take in the clock frequency information.
14. The device in accordance with claim 13 , wherein said switch timing signal is generated at a boundary between items included in the baseband signal, which is divided by a preselected cycle division, and subjects of detection of the optimum phase information.