Complementary bit resistance memory sensor and method of operation

1. A programmable resistance memory device, comprising:

a first and second digit line;

first and second programmable resistance memory elements associated with a single memory cell for respectively storing complementary binary digit values of a data bit as different resistance values;

first and second access devices for respectively coupling said first and second memory elements to said first and second digit lines; and

a sense amplifier having inputs respectively coupled to said first and second digit lines for reading said data bit stored as a resistance value in one of said memory elements.

2. The device as in claim 1 further comprising a precharge circuit for precharging said digit lines to a common precharge voltage prior to a read operation.

3. The device as in claim 1 further comprising a pair of row lines respectively coupled to said first and second access devices; and

circuitry for simultaneously activating said first and second row lines and therefore activating said first and second access devices.

4. The device as in claim 3 wherein said first and second access devices are access transistors.

5. The device as in claim 3 wherein when said access devices are activated, said precharge voltage on said digit lines discharges through a respective resistance of said first and second resistance-based memory elements, said sense amplifier determining whether said one of said memory elements is storing a high or low resistance state and outputting a binary value corresponding to the stored resistance state.

6. The device as in claim 2 wherein said digit lines have an associated parasitic capacitance which stores said precharge voltage.

7. The device as in claim 2 wherein said parasitic capacitance stores a voltage value which is larger than said precharge voltage.

8. The device as in claim 3 wherein said row lines are activated in a manner which prevents an automatic refresh of at least one of said memory elements during a read operation.

9. The device as in claim 1 wherein said first and second memory elements are in different memory arrays.

10. The device as in claim 2 further comprising an equilibrate circuit for equilibrating the voltage on said digit lines.

11. A memory device comprising:

a plurality of pairs of first and second programmable resistance memory cells, each pair of memory cells comprising:

first and second programmable resistance memory elements associated with a single memory cell for respectively storing complementary binary digit values of a data bit as different resistance values;

first and second access devices for respectively coupling said first and second memory elements to first and second digit lines; and

a sense amplifier having inputs respectively coupled to said first and second digit lines for reading said data bit stored as a resistance value in one of said memory elements.

12. The device as in claim 11 further comprising a precharge circuit for precharging said digit lines to a common precharge voltage prior to a read operation.

13. The device as in claim 11 further comprising a pair of row lines respectively coupled to said first and second access devices; and

circuitry for simultaneously activating said first and second row lines and therefore activating said first and second access devices.

14. The device as in claim 13 wherein said first and second access devices are access transistors.

15. The device as in claim 13 wherein when said access devices are activated, said precharge voltage on said digit lines discharges through a respective resistance of said first and second programmable resistance memory elements, said sense amplifier determining whether said one of said memory elements is storing a high or low resistance state and outputting a binary value corresponding to the stored resistance state.

16. The device as in claim 15 wherein said digit lines have an associated parasitic capacitance which stores said precharge voltage.

17. The device as in claim 15 wherein said parasitic capacitance stores a voltage value which is larger than said precharge voltage.

18. The device as in claim 11 wherein said first and second memory elements are in a common memory array.

19. The device as in claim 11 wherein said first and second memory elements are in different memory arrays.

20. The device as in claim 12 further comprising an equilibrate circuit for equilibrating the precharge voltage on said digit lines.

21. The device as in claim 11 wherein said memory device is provided on a memory module.

22. The device as in claim 21 wherein said memory module is a plug-in memory module.

23. A computer system comprising:

a processor;

a memory system coupled to said processor, said memory system comprising:

a first and second digit line;

first and second programmable resistance memory elements associated with a single memory cell for respectively storing complementary binary digit values of a data bit as different resistance values;

first and second access devices for respectively coupling said first and second programmable resistance memory elements to said first and second digit lines; and

a sense amplifier having inputs respectively coupled to said first and second digit lines for reading said data bit stored as a resistance value in one of said memory elements.

24. The system as in claim 23 further comprising a precharge circuit for precharging said digit lines to a common precharge voltage prior to a read operation.

25. The system as in claim 23 further comprising a pair of row lines respectively coupled to said first and second access devices; and

circuitry for simultaneously activating said first and second row lines and therefore activating said first and second access devices.

26. The system as in claim 25 wherein said first and second access devices are access transistors.

27. The system as in claim 25 wherein when said access devices are activated, said precharge voltage on said digit lines discharges through a respective resistance of said first and second memory elements, said sense amplifier determining whether said one of said memory elements is storing a high or low resistance state and outputting a binary value corresponding to the stored resistance state.

28. The system as in claim 24 wherein said digit lines have an associated parasitic capacitance which stores said precharge voltage.

29. The system as in claim 24 wherein said parasitic capacitance stores a voltage value which is larger than said precharge voltage.

30. The system as in claim 23 wherein said first and second memory elements are in a common memory array.

31. The system as in claim 23 wherein said first and second memory elements are in different memory arrays.

32. The system as in claim 24 further comprising an equilibrate circuit for equilibrating the voltage on said digit lines.