Integrated circuit incorporating protection from power supply attacks
View Patent ↗An integrated circuit including: non-volatile memory for containing secret information; and a detection unit for preventing at least one form of power supply attack on the secret information, the detection unit comprising: a first comparator having a first input connected to a first reference voltage and a second input connected to a power supply line, the first comparator being configured to output a first detection signal when a power supply voltage moves beyond a first predetermined limit determined by the first reference voltage; and an output to provide a signal to delete, overwrite, or otherwise render unreadable at least the secret information in the memory when the first detection signal is output by the first comparator.
1. An integrated circuit including: non-volatile memory for storing secret information and an indicator that the secret information is stored therein; and a detection unit for preventing at least one form of power supply attack on the secret information, the detection unit comprising:
a comparator having a first input connected to a reference voltage and a second input connected to a power supply line, the comparator being configured to output a detection signal when a power supply voltage is under a predetermined limit determined by the reference voltage; and
an output connected into a reset line of the integrated circuit, the output providing a reset signal to first delete, overwrite, or otherwise render unreadable the indicator and then delete, overwrite, or otherwise render unreadable the secret information in the memory when the detection signal is output by the comparator,
wherein the reset signal is provided when the power supply voltage drops below the predetermined limit due to a power-down of the integrated circuit.
2. An integrated circuit according to claim 1 , wherein the reset line is a tamper detection line, the tamper detection line responding to the signal to delete, overwrite, or otherwise render unreadable at least the secret information in the memory.
3. An integrated circuit according to claim 1 , wherein the detection unit is implemented in CMOS.
4. An integrated circuit according to claim 1 , wherein the detection unit is covered by a tamper detection line, or by a tamper prevention line, or both.