Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register
A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.
1. A semiconductor memory having a synchronous operation mode or an asynchronous operation mode for an external clock, the memory comprising:
a synchronous/asynchronous mode setting section for generating a signal for causing the semiconductor memory to make a transition between the synchronous operation mode and the asynchronous operation mode; and
a state selection section for choosing, by selecting an internal signal the level of which changes in a power-down state or an internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to the synchronous/asynchronous mode setting section, whether the semiconductor memory should make a transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode.
2. The semiconductor memory according to claim 1 , wherein the internal signal the level of which changes in the power-down state is a starter signal for an internal power supply circuit.
3. The semiconductor memory according to claim 1 , wherein the internal signal the level of which does not change in the power-down state is a starter signal for an external power supply.
4. The semiconductor memory according to claim 1 , wherein instructions to select the internal signal the level of which changes in the power-down state are given by the state selection signal to cause the semiconductor memory to make the transition from the power-down state to the standby state in the asynchronous mode.
5. The semiconductor memory according to claim 1 , wherein the internal signal the level of which does not change in the power-down state is generated at power-up time.
6. The semiconductor memory according to claim 1 , further comprising an external clock buffer, wherein:
the signal for causing the semiconductor memory to make the transition between the synchronous operation mode and the asynchronous operation mode is inputted to the external clock buffer; and
the external clock buffer stops accepting the external clock in the asynchronous operation mode.