IP Library Granted Patent US 7,098,471
Granted Patent B2
US 7,098,471 · App. 10/867,037 · Granted Aug 29, 2006

Semiconductor quantum well devices and methods of making the same

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Quick Facts
Patent No.
US 7,098,471
App. No.
10/867,037
Granted
Aug 29, 2006
Kind
B2
Abstract

Semiconductor quantum well devices and methods of making the same are described. In one aspect, a device includes a quantum well structure that includes semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells. Each of the quantum wells includes a quantum well layer interposed between barrier layers. One of the semiconductor layers that functions as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells. Another of the semiconductor layers that functions as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.

Claims (29)

1. A device, comprising:

a quantum well structure comprising semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells, each of the quantum wells comprising a quantum well layer interposed between barrier layers, wherein one of the semiconductor layers functioning as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells, and another of the semiconductor layers functioning as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.

2. The device of claim 1 , wherein ones of the semiconductor layers function as barrier layers and quantum well layers for conduction band electrons.

3. The device of claim 2 , wherein the semiconductor layer functioning as the quantum well layer for the conduction band electrons also functions as the quantum well layer for the heavy-holes.

4. The device of claim 3 , wherein direct electron-to-heavy-hole transitions occur across a Type I energy-band alignment, and direct electron-to-light-hole transitions occur across a Type II energy-band alignment.

5. The device of claim 2 , wherein ones of the semiconductor layers functioning as the barrier layers for the conduction band electrons also function as the quantum well layers for the light holes.

6. The device of claim 1 , wherein the semiconductor layer functioning as the quantum well layer for the light hole quantum well is under a first type of strain, and the semiconductor layer functioning as the quantum well layer of the heavy hole quantum well is under a second type of strain different from the first type of strain.

7. The device of claim 6 , wherein the semiconductor layers includes alternating layers of different In x Ga 1-x As y P 1-y composition, where 0≦x≦1 and 0≦y≦1.

8. The device of claim 7 , wherein y has a substantially constant value in the alternating layers.

9. The device of claim 7 , wherein y has a value that varies across the alternating layers.

10. The device of claim 7 , wherein the layer functioning as the quantum well layer of the light-hole quantum well is under tensile strain, and the layer functioning as the quantum well layer of the heavy-hole quantum well is under compressive strain.

11. The device of claim 6 , wherein the semiconductor layers includes alternating layers of different In 1-x-y Al x Ga y As composition, where 0≦x≦1 and 0≦y≦1.

12. The device of claim 1 , wherein each of the light-hole and heavy-hole quantum wells has a respective lowest band state at substantially equal relative energy levels.

13. The device of claim 1 , wherein TM mode optical absorption by the light-hole quantum well is substantially equal in magnitude to TE mode optical absorption by the heavy-hole quantum well for a target optical wavelength.

14. The device of claim 13 , wherein levels of TM mode optical absorption and TE mode optical absorption differ by at most 1 dB (decibel) for the target optical wavelength.

15. The device of claim 1 , wherein each of the semiconductor layers has a respective thickness ranging from about 5 nm to about 12 nm.

16. The device of claim 1 , further comprising:

first and second electrodes;

first and second cladding regions disposed between the first and second electrodes; and

an active region disposed between the first and second cladding regions and including the semiconductor quantum well structures.

17. The device of claim 16 wherein the semiconductor quantum well structure is incorporated in a light absorption region configured to absorb light traveling therethrough in an amount responsive to an electrical signal applied across the first and second electrodes.

18. A method of making a device, comprising:

forming a quantum well structure comprising semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells, each of the quantum wells comprising a quantum well layer interposed between barrier layers, wherein one of the semiconductor layers functioning as a barrier layer of one of the light-hole quantum well layers also functions as the quantum well layer of one of the heavy-hole quantum wells, and another of the semiconductor layers functioning as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.

19. The method of claim 18 , wherein ones of the semiconductor layers function as barrier layers and quantum well layers for a conduction band electron quantum well.

20. The method of claim 18 , further comprising introducing a first type of strain into the semiconductor layer functioning as the quantum well layer of the light hole quantum well, and introducing a second type of strain different from the first type of strain into the semiconductor layer functioning as the quantum well layer of the heavy hole quantum well.

21. The method of claim 18 , further comprising:

forming first and second electrodes;

forming first and second cladding regions disposed between the first and second electrodes; and

forming an active region disposed between the first and second cladding regions and including the semiconductor quantum well structures.

Assignments (9)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0672 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0199 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2004
From: RANGANATH, TIRUMALA R.; ZHU, JINTIAN
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 015499/0368 →