Method for fabricating polycrystalline silicon liquid crystal display device
View Patent ↗A method of fabricating integral-type LCD devices incorporating polysilicon-type TFTs reduces the number of masks required to fabricate a thin film transistor (TFT). According to the method, a lightly-doped-drain (LDD) type TFT is formed using a single photoresist pattern and a photoresist ashing technique.
1. A method for fabricating a thin film transistor in a liquid crystal display (LCD) device, comprising:
forming a polysilicon layer on a substrate;
forming a gate insulating layer on the polysilicon layer;
forming a metal layer on the gate insulating layer;
forming a first photoresist pattern on the metal layer;
patterning the metal layer into a gate electrode using the first photoresist pattern as a mask;
patterning the polysilicon layer and the gate insulating layer to form an active layer;
removing a portion of the first photoresist pattern thereby forming a second photoresist pattern;
firstly implanting impurity ions into the active layer using the second photoresist pattern as a mask;
removing a portion of the gate insulating layer formed on the active layer after said firstly implanting impurity ions into the active layer;
secondly implanting impurity ions at a high concentration into the active layer exposed by removing the gate insulating layer;
forming a source/drain electrode on a portion of the active layer implanted with the high concentration of impurity ions; and
forming a pixel electrode electrically contacting the drain electrode.
2. The method of claim 1 , further including forming a buffer layer on the substrate prior to forming the polysilicon layer.
3. The method of claim 1 , wherein the step for forming the polysilicon layer comprises:
forming an amorphous silicon layer on the substrate; and
crystallizing the amorphous silicon layer.
4. The method of claim 3 , wherein the crystallizing includes annealing the amorphous silicon layer.
5. The method of claim 4 , wherein the annealing includes irradiating light from an excimer laser onto the amorphous silicon layer.
6. The method of claim 1 , wherein patterning the metal layer includes undercutting the first photoresist pattern such that the gate electrode is smaller than the first photoresist pattern.
7. The method of claim 6 , wherein patterning the metal layer includes wet-etching the metal layer.
8. The method of claim 1 , wherein removing a portion of the first photoresist pattern includes ashing the first photoresist pattern.
9. The method of claim 1 , wherein patterning the polysilicon layer and gate insulating layer includes dry-etching the polysilicon layer and the gate insulating layer by applying the first photoresist pattern as a mask.
10. The method of claim 1 , wherein firstly implanting impurity ions includes forming LDD region within the active layer.
11. The method of claim 10 , wherein the LDD region is formed by diffusion of the firstly implanted impurity ions.
12. The method of claim 1 , wherein removing a portion of the gate insulating layer includes dry-etching the gate insulating layer using the second photoresist pattern as a mask.
13. The method of claim 1 , wherein the second photoresist pattern is larger than the gate electrode.
14. The method of claim 1 , wherein forming the pixel electrode includes:
forming a passivation layer on the source/drain electrode;
forming a contact hole within the passivation layer, wherein the contact hole exposes the drain electrode; and
forming a pixel electrode within the contact hole to electrically contact the drain electrode.
15. The method of claim 1 , wherein the firstly implanted impurity ions include atoms of a Group V element.