On chip capacitor
View Patent ↗A high capacity silicon capacitor formed on an integrated circuit substrate includes a metal portion on the substrate; a silicon nitride (SiN) portion sputtered on the metal; a silicon (Si) portion sputtered on the silicon nitride portion, another SiN layer and finally a metal layer. The SiN layers are for increased isolation and are optional.
1. A method for forming a silicon capacitor, comprising:
depositing a metal portion on a substrate;
sputtering silicon with nitrogen gas to form a silicon nitride (SiN) portion directly on the metal portion;
removing nitrogen gas flow and sputtering a silicon (Si) portion on the SiN portion.
2. The method of claim 1 , further comprising forming a sandwich with a plurality of layers of SiN and Si.
3. The method of claim 2 , further comprising developing a metal layer adjacent to the sandwich.
4. The method of claim 1 , wherein the silicon nitride decreases leakage.
5. The method of claim 1 , further comprising depositing a second silicon nitride portion.
6. The method of claim 1 , further comprising depositing a second metal portion.
7. The method of claim 1 , further comprising:
adding nitrogen gas again to cap the Si portion with SiN; and
depositing metal on the SiN cap.
8. The method of claim 1 , further comprising forming a layer of SiN comprising the SiN portion and a layer of Si comprising the Si portion, wherein each of the layers of SiN and Si formed is approximately forty angstroms thick.
9. A method for forming a silicon capacitor, comprising:
depositing a first metal portion on a substrate;
sputtering an insulator portion directly on the metal portion, the insulator portion comprising a sandwich formed with a plurality of alternating silicon nitride (SiN) and silicon (Si) layers; and
depositing a second metal portion directly on the insulator portion.
10. The method of claim 9 , wherein the Si portion comprises amorphous silicon.
11. The method of claim 9 , further comprising forming the silicon capacitor on an integrated circuit having an analog portion and a digital portion.
12. The method of claim 11 , wherein the integrated circuit comprises a multi-mode wireless communication device.
13. A method of forming a silicon capacitor comprising:
depositing a first metal portion on a substrate;
forming a first silicon nitride (SiN) portion directly over the first metal portion;
forming a silicon (Si) portion directly over the first SIN portion;
forming a second SiN portion directly over the Si portion; and
forming a second metal portion directly over the second SiN portion to form the silicon capacitor for storing charge in an integrated circuit.
14. The method of claim 13 , wherein forming the first SiN portion comprises sputtering silicon with nitrogen gas.
15. The method of claim 13 , further comprising forming the silicon capacitor using a complementary metal oxide semiconductor (CMOS) process.
16. The method of claim 13 , further comprising forming the silicon capacitor on a mixed signal integrated circuit.
17. The method of claim 13 , further comprising forming a sandwich layer formed of a SiN layer and a Si layer on the Si portion.
18. The method of claim 13 , further comprising:
forming a second Si portion directly over the second SiN portion; and
forming a third SiN portion directly over the second Si portion.
19. The method of claim 13 , wherein the silicon capacitor has a capacitance substantially greater than a similarly sized capacitor formed of silicon dioxide.