Rate dematching processor
View Patent ↗(3n+1)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a first memory 102 , (3n+2)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a second memory 103 , and (3n+3)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a third memory 104 . Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue 108 , a first parity bit queue 109 , and a second parity bit queue 110 , respectively, to control data supply to the rate dematching circuits 111 and 112 by these queues 108, 109 and 110.
1. A processor which performs a rate dematching process with respect to rate matched data including information bit, first parity bit and second parity bit, comprising:
one or a plurality of memories which store the data input;
data reading out means for reading out the information bit, first parity bit and second parity bit from said one or a plurality of memories every 3n bits, said n being a natural number; and
data holding means provided at least for each of the information bit, first parity bit and second parity bit, for holding the data read out by said data reading out means in order to control data supply to a rate dematching circuit.
2. A processor which performs a rate dematching process with respect to rate matched data including information bit, first parity bit and second parity bit, comprising:
a first memory which stores (3n+1)th input data, a second memory which stores (3n+2)th input data and a third memory which stores (3n+3)th input data, wherein n is an integer not more than M/3−1 and M is multiples of 3;
data reading out means for reading out the information bit, first parity bit and second parity bit from each of said first to third memories every 3 bits; and
an information bit queue, a first parity bit queue and second parity bit queue which hold information bit, first parity bit and second parity bit read out every 3 bits by said data reading out means, respectively to control data supply to a rate dematching circuit.
3. A processor which performs a rate dematching process with respect to rate matched data including information bit, first parity bit and second parity bit, comprising:
a memory which stores input data in the order of inputting;
data reading out means for reading out the information bit, first parity bit and second parity bit from said memory every 3 bits; and
an information bit queue, a first parity bit queue and second parity bit queue which hold information bit, first parity bit and second parity bit read out every 3 bits, respectively to control data supply to a rate dematching circuit.
4. A processor which performs rate dematching with respect to rate matched data including information bit, first parity bit and second parity bit, comprising:
a first memory which stores (6n+1)th input data, a second memory which stores (6n+2)th input data, a third memory which stores (6n+3)th input data, a fourth memory which stores (6n+4)th input data, a fifth memory which stores (6n+5)th input data, and sixth memory which stores (6n+6)th input data, wherein n is an integer not more than M/6−1 and M is multiples of 6;
data reading out means for reading out the information bits, first parity bits, and second parity bits from each of said first to sixth memories every 6 bits, the information bits, first parity bits and second parity bits read out every 6 bits being divided into a first block and a second block;
a first block information bit queue, a first block first parity bit queue, and a first block second parity bit queue which hold first block information bit, first block first parity bit and first block second parity bit, respectively, to control data supply to a rate dematching circuit; and
a second block information bit queue, a second block first parity bit queue and a second block second parity bit queue which hold second block information bit, second block first parity bit and second block second parity bit, respectively, to control data supply to said rate dematching circuit.