Thin film transistor with self-aligned intra-gate electrode
View Patent ↗A thin film transistor for use in an active matrix liquid crystal display includes a substrate, a source and a drain regions, and at least a gate electrode. The substrate includes therein a plurality of intrinsic regions, at least one first doped region and two second doped regions. The first doped region is disposed between the plurality of intrinsic regions. The plurality of intrinsic regions are linked together to form a connection structure via the first doped region, and the two second doped regions are disposed at both ends of the connection structure, respectively. The source and the drain regions are coupled to the two second doped regions disposed at both ends of the connection structure, respectively. The gate electrode is disposed over the plurality of intrinsic regions, such that the periphery of each of the plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.
1. A thin film transistor for use in an active matrix liquid crystal display, comprising:
a substrate comprising therein a plurality of intrinsic regions, at least one first doped region and two second doped regions, said first doped region being disposed between said plurality of intrinsic regions, wherein said plurality of intrinsic regions are linked together to form a connection structure via said first doped region, and said two second doped regions are disposed at both ends of said connection structure, respectively;
a source and a drain region coupled to said two second doped regions disposed at both ends of said connection structure, respectively; and
at least one gate electrode disposed over said plurality of intrinsic regions, such that the periphery of each of said plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.
2. The thin film transistor according to claim 1 wherein said substrate comprises a polysilicon layer.
3. The thin film transistor according to claim 2 wherein said plurality of intrinsic regions, said first doped region and said second doped region are formed in said polysilicon layer.
4. The thin film transistor according to claim 1 wherein said first doped region and said second doped region are formed by implanting a first and a second dopant concentrations of phosphorus thereinto, respectively.
5. The thin film transistor according to claim 4 wherein said second dopant concentration is greater than said first dopant concentration.
6. The thin film transistor according to claim 1 further comprising a gate oxide layer between said intrinsic regions and said corresponding gate electrode.
7. The thin film transistor according to claim 1 wherein said gate electrode is arranged in a Π-shaped configuration.
8. The thin film transistor according to claim 7 wherein the characteristic length of said gate electrode is less than 7 μm.
9. The thin film transistor according to claim 1 wherein said gate electrode is arranged in an L-shaped configuration.
10. The thin film transistor according to claim 9 wherein the characteristic length of said gate electrode is less than 5 μm.
11. The thin film transistor according to claim 1 wherein said gate electrode is arranged in an I-shaped configuration.
12. The thin film transistor according to claim 11 wherein the characteristic length of said gate electrode is less than 5 μm.
13. The thin film transistor according to claim 1 wherein said gate electrode is arranged in an E-shaped configuration.
14. The thin film transistor according to claim 13 wherein the characteristic length of said gate electrode is less than 7 μm.
15. A thin film transistor, comprising:
a substrate comprising therein N intrinsic regions, (N−1) first doped regions and two second doped regions, said (N−1) first doped regions being disposed between said N intrinsic regions in a staggered form, said two second doped regions being disposed outside the first one and the Nth one of said N intrinsic regions, wherein N is an integer larger than or equal to 2;
a source and a drain regions coupled to said two second doped regions, respectively; and
at least one gate electrode disposed over said N intrinsic regions, such that the periphery of each of said N intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.
16. The thin film transistor according to claim 15 wherein said substrate is a substrate having a polysilicon layer.
17. The thin film transistor according to claim 15 wherein said first doped region and said second doped region are formed by implanting a first and a second dopant concentrations of phosphorus thereinto, respectively.
18. The thin film transistor according to claim 17 wherein said second dopant concentration is greater than said first dopant concentration.
19. The thin film transistor according to claim 15 wherein said gate electrode is arranged in a Π-shaped, an L-shaped, an I-shaped or an E-shaped configuration.
20. The thin film transistor according to claim 19 wherein the characteristic length of said gate electrode is less than 7 μm when said gate electrode is arranged in a Π-shaped or an E-shaped configuration, and the characteristic length of said gate electrode is less than 5 μm when said gate electrode is arranged in an L-shaped or an I-shaped configuration.