Wireless device having a distinct hardware video accelerator to support video compression and decompression

1 . A video processor within a wireless terminal, comprising:

a video interface that receives incoming video information and that provides outgoing video information;

a processing module operably coupled to the video interface;

a video accelerator operably coupled to the processing module;

a motion processing co-processor operably coupled to the processing module; and

wherein processing of the incoming video information and the outgoing video information is performed by the combination of the processing module, video co-processor and the video accelerator module.

2 . The video processor of claim 1 , wherein the motion co-processor performs Sum of Absolute Difference (SAD) operations, half-pixel interpolation, motion compensation, motion separation between interframes when encoding video information.

3 . The video processor of claim 1 , wherein the motion co-processor performs half-pixel interpolation and motion compensation when decoding video information.

4 . The video processor of claim 1 , wherein the video accelerator module, when encoding video information, performs:

Fast Discrete Cosine Transform (FDCT) operations;

Quantization (QUAN) operations;

Inverse Quantization (IQUAN) operations; and

Inverse Discrete Cosine Transform (IDCT) operations.

5 . The video processor of claim 1 , wherein the video accelerator module, when decoding video information, performs:

Inverse Quantization (IQUAN) operations; and

Inverse Discrete Cosine Transform (IDCT) operations.

6 . The video processor of claim 1 , wherein the processing module performs:

zig-zag operations;

Un-zig-zag operations;

Run Length Coding/Variable Length Coding (RLC/VLC) operations;

VLC/RLC decoding operations; and

Bit stream formatting operations.

7 . The video processor of claim 1 , wherein a mode of operation of the video accelerator module is directed by a control interface operably coupled to the video accelerator module.

8 . The video processor of claim 7 , wherein the mode of operation comprises either a decode mode or an encode mode.

9 . The video processor of claim 7 , wherein the control interface comprises:

a configuration register operably coupled to the processing module, wherein a state of the configuration register defines the mode of operation of the video accelerator module;

a buffer setup register; and

a buffer access register.

10 . The video processor of claim 9 , wherein states of the buffer setup register define an address and format of data received by and outputted from the video accelerator module.

11 . The video processor of claim 10 , wherein the video accelerator module writes/reads data to/from the buffer access register.

12 . The video processor of claim 11 , wherein the format of data received by and outputted from the video accelerator module comprise:

MPEG 4;

MPEG 4 with an H.263 quantization scheme; or

JPEG.

13 . The video processor of claim 1 , wherein the wireless terminal operates according to the GSM standard.

14 . A wireless terminal that comprises:

a Radio Frequency (RF) front end;

a baseband processor communicatively coupled to the RF front end;

a video input device to capture incoming video information;

a video display device to display outgoing video information;

a video interface that receives incoming video information and that provides outgoing video information; and

a video processor that further comprises:

a processing module operably coupled to the video interface;

a motion co-processor operably coupled to the processing module;

a video accelerator module operably coupled to the processing module; and

wherein processing of the incoming video information and the outgoing video information is performed by the combination of the processing module, motion co-processor and video accelerator module.

15 . The wireless terminal of claim 14 , wherein the motion co-processor performs Sum of Absolute Difference (SAD) operations, half-pixel interpolation, motion compensation, motion separation between interframes when encoding video information.

16 . The wireless terminal of claim 14 , wherein the motion co-processor performs half-pixel interpolation and motion compensation when decoding video information.

17 . The wireless terminal of claim 14 , wherein the video accelerator module, when encoding video information, performs:

Fast Discrete Cosine Transform (FDCT) operations;

Quantization (QUAN) operations;

Inverse Quantization (IQUAN) operations; and

Inverse Discrete Cosine Transform (IDCT) operations.

18 . The wireless terminal of claim 14 , wherein the video accelerator module, when decoding video information, performs:

Inverse Quantization (IQUAN) operations; and

Inverse Discrete Cosine Transform (IDCT) operations.

19 . The wireless terminal of claim 14 , wherein the processing module performs:

zig-zag operations;

Un-zig-zag operations;

Run Length Coding/Variable Length Coding (RLC/VLC) operations;

VLC/RLC decoding operations; and

Bit stream formatting operations.

20 . The wireless terminal of claim 14 , wherein a mode of operation of the video accelerator module is directed by a control interface operably coupled to the video accelerator module.

21 . The wireless terminal of claim 20 , wherein the mode of operation comprises either a decode mode or an encode mode.

22 . The wireless terminal of claim 14 , wherein the video interface performs pre-processing functions and post-processing functions.

23 . The wireless terminal of claim 14 , wherein the format of data received by and outputted from the video accelerator module comprise:

MPEG 4;

MPEG 4 with an H.263 quantization scheme; or

JPEG.

24 . The wireless terminal of claim 14 , wherein the wireless terminal operates according to the GSM standard.

25 . A method to process video information within a wireless terminal comprising:

receiving video information at a video processing engine;

determining a mode of operation of the video processing engine from a format of the video operation; and

dividing the processing of the video information between a processing module, motion co-processor and a video accelerator module.

26 . The method of claim 25 , wherein the motion co-processor performs Sum of Absolute Difference (SAD) operations, half-pixel interpolation, motion compensation, motion separation between interframes when encoding video information.

27 . The method of claim 25 , wherein the motion co-processor performs half-pixel interpolation and motion compensation when decoding video information.

28 . The method of claim 25 , wherein the video accelerator module, when encoding video information, performs:

Fast Discrete Cosine Transform (FDCT) operations;

Quantization (QUAN) operations;

Inverse Quantization (IQUAN) operations; and

Inverse Discrete Cosine Transform (IDCT) operations.

29 . The method of claim 25 , wherein the video accelerator module, when decoding video information, performs:

Inverse Quantization (IQUAN) operations; and

Inverse Discrete Cosine Transform (IDCT) operations.

30 . The method of claim 25 , wherein the processing module performs:

zig-zag operations;

Un-zig-zag operations;

Run Length Coding/Variable Length Coding (RLC/VLC) operations;

VLC/RLC decoding operations; and

Bit stream formatting operations.

31 . The method of claim 25 , wherein the format of video information received by and outputted from the video processing engine comprise:

MPEG 4;

MPEG 4 with an H.263 quantization scheme; or

JPEG.

32 . The method of claim 25 , wherein the wireless terminal operates according to the GSM standard.