Semiconductor integrated circuit device

1. A semiconductor integrated circuit device comprising:

a first circuit block connected to a first node;

a second circuit block connected to a second node; and

a comparator to compare the first potential of the first node and a second potential of the second node,

wherein the second circuit block is provided on the same semiconductor chip as the first circuit block,

wherein a first supply current in a quiescent state flows through the first node and the first circuit block, and

wherein a second supply current in a quiescent state flows through the second node and the second circuit blocks,

a third node;

a first MOS transistor of a first conductivity type having a source-drain path between the first node and the third node; and

a second MOS transistor of the first conductivity type having a source-drain path between the second node and the third node,

wherein a gate of the first MOS transistor is connected to a gate of the second MOS transistor, and

wherein a gate of the second MOS transistor is connected to a drain of the second MOS transistor.

2. The semiconductor integrated circuit device according to claim 1 ,

wherein a number of gates included in the first circuit block is m,

wherein a number of gates included in the second circuit block is n, and

wherein a mirror ratio of a current mirror formed by the first MOS transistor and the second MOS transistor is k*m:n, k being a predetermined constant.

3. The semiconductor integrated circuit device according to claim 1 ,

wherein the second circuit block is a dummy circuit block.

4. The semiconductor integrated circuit device according to claim 1 , further comprising:

a power supply line; and

a third MOS transistor of the first conductivity type having a source-drain path between the third node and the power supply line,

wherein the third MOS transistor is controlled to be in an ON state when an IDDQ test is executed.

5. The semiconductor integrated circuit device according to claim 4 , further comprising:

a fourth MOS transistor of the first conductivity type having a source-drain path between the first node and the power supply line,

wherein the fourth MOS transistor is controlled to be in an OFF state when the first circuit block is controlled to be in a standby state.

6. The semiconductor integrated circuit device according to claim 1 , further comprising:

an output pin,

wherein the output pin selectively outputs an output from the first circuit block or an output from the comparator.

7. A testing method of a semiconductor integrated circuit device, comprising steps of:

providing the semiconductor integrated circuit device including a first circuit block connected to a first node and a second circuit block connected to a second node formed on the same semiconductor chip; and

comparing a first potential of the first node and a second potential of the second node;

wherein a first supply current in a quiescent state flows to the first node and the first circuit block and a second supply current in a quiescent state flows to the second node and the second circuit block.

wherein the semiconductor chip includes a third node, a first MOS transistor of a first conductivity type having a source-drain path between the first node and the third node and a second MOS transistor of the first conductivity type having a source-drain oath between the second node and the third node;

wherein a gate of the first MOS transistor is connected to a gate of the second MOS transistor, and

wherein a gate of the second MOS transistor is connected to a drain of the second MOS transistor.

8. The testing method according to claim 7 ,

wherein a number of gates included in the first circuit block is m,

wherein a number of gates included in the second circuit block is n, and

wherein a mirror ratio of a current mirror formed by the first MOS transistor and the second MOS transistor is k*m:n, k being a predetermined constant.