LDMOS transistor having gate shield and trench source capacitor
An LDMOS transistor includes a trench source capacitor structure and a gate-drain shield which can be interconnected whereby the source capacitor can be grounded to provide an RF ground for the shield and whereby the RF shield can have a positive DC voltage bias to enhance laterally diffused drain conductance without increasing doping therein. The trench capacitor structure can include one or more adjacent trenches to increase capacitor plate area.
1 . A LDMOS transistor comprising:
a) a semiconductor substrate having a first major surface,
b) a source region and a drain region formed in the first major surface and spaced apart by a channel region,
c) a gate positioned over the channel region and separated therefrom by a gate dielectric layer,
d) a gate shield overlying a portion of the gate and separated therefrom by a shield dielectric layer, and
e) a source capacitor including the source region as part of one capacitor plate, a capacitor dielectric layer, and a second capacitor plate on the dielectric layer, the source capacitor formed in at least one trench in the first major surface and extending into the substrate.
2 . The LDMOS transistor as defined by claim 1 wherein the substrate includes a P+ substrate and a P− epitaxial layer on the substrate, the first major surface being a surface of the P− epitaxial layer.
3 . The LDMOS transistor as defined by claim 2 and further including a P-doped sinker region extending through the epitaxial layer to the P+ substrate, the one capacitor plate including a conductive layer connected to the source region and to the substrate.
4 . The LDMOS transistor as defined by claim 3 and further including a metal layer on a second major surface of the substrate opposite from the first major surface, the one capacitor plate being ohmically connected to the second major surface.
5 . The LDMOS transistor as defined by claim 4 wherein the conductor layer of the second capacitor plate comprises a stacked layer of TiW, TiWN, TiW, and Au.
6 . The LDMOS transistor as defined by claim 4 , wherein the gate shield comprises the stacked layer of TiW, TiWN, TiW, and Au.
7 . The LDMOS transistor as defined by claim 6 wherein the second capacitor plate comprises a stacked layer of TiW, TiWN, TiW, and Au.
8 . The LDMOS transistor as defined by claim 7 wherein the second capacitor plate and the gate shield are formed from the same stacked layer.
9 . The LDMOS transistor as defined by claim 7 wherein the metal layer on the second major surface is DC grounded.
10 . The LDMOS transistor as defined by claim 1 wherein the one capacitor plate is DC grounded.
11 . The LDMOS transistor as defined by claim 1 wherein the source capacitor is formed in at least two adjacent trenches in the first major surface and extending into the substrate.
12 . The LDMOS transistor as defined by claim 1 wherein the substrate includes a N+ substrate, and a P− epitaxial layer on the substrate with a P+ buried layer in the epitaxial layer.
13 . The LDMOS transistor as defined by claim 1 and further comprising:
f) a conductor interconnecting the second capacitor plate and the gate shield.
14 . The LDMOS transistor as defined by claim 1 wherein the one capacitor plate further includes a silicide layer on the source region.
15 . The LDMOS transistor as defined by claim 14 wherein the one capacitor plate further including plated metal on the silicide layer.