Granted Patent B1

US 6,980,140 · App. 10/870,054 · Granted Dec 27, 2005

Abstract

Claims (26)

1. A receiver comprising:

a flash analog to digital converter (ADC);

a symbol decoder, which receives input from said ADC and operates on groups of bits of a fixed bit length, each group of bits comprising a target bit and bits adjacent in time to said target bit, said bits adjacent in time to said target bit being assumed to affect a voltage of said target bit before decoding due to inter-symbol interference;

a link quality indicator, which receives input from said symbol decoder and generates link quality indications therefrom; and

reference voltage adjuster, which receives input from said ADC and the link quality indications from the link quality indicator and, responsive thereto outputs to a control input to said ADC for selectively adjusting one or more reference voltages of said ADC.

2. The receiver of claim 1 wherein said symbol decoder is a Viterbi decoder.

3. The receiver of claim 1 wherein said link quality indications indicate link quality at a voltage slicing level of said ADC and said reference voltage adjuster adjusts a reference voltage level associated with said voltage slicing level when said link quality indications do not meet a threshold quality level.

4. The receiver of claim 1 wherein said link quality indicator is an error detector.

5. The receiver of claim 4 wherein said reference voltage adjuster operates to adjust a given reference voltage when a rate of errors at a voltage slicing level of said ADC associated witb said given reference voltage level exceeds a threshold.

6. The receiver of claim 4 wherein said error detector is a forward error corrector (FEC) having an output which inputs into said reference voltage adjuster.

7. The receiver of claim 4 wherein said error detector comprises a portion of said reference voltage adjuster.

8. The receiver of claim 1 wherein said reference voltage adjuster determines probability information comprising a probability of occurrence for all possible groups of bits of said fixed bit length for each of said reference voltages and wherein said probability information is output to said symbol decoder.

9. The receiver of claim 8 wherein said reference voltage adjuster holds a current channel impulse response model and said probability information is derived from said current channel impulse response model.

10. The receiver of claim 9 wherein said reference voltage adjuster updates said model, or selects a different model, responsive to indications from said link quality indicator.

11. A receiver comprising:

a flash analog to digital converter (ADC);

decoding means responsive to said ADC to decode symbols, said decoding means operating on groups of bits of a fixed bit length, each group of bits comprising a target bit and bits adjacent in time to said target bit, said bits adjacent in time to said target bit being assumed to affect a voltage of said target bit before decoding due to inter-symbol interference;

link quality detecting means responsive to said decoding means to detect symbol decoding errors; and

a channel estimation block responsive to said ADC and said symbol decoding errors for adjusting reference voltages of said ADC.

12. In a receiver utilising a flash analog to digital converter (ADC), a method of improving link quality comprising:

adjusting a reference voltage for a voltage slicing level of said ADC when a decoding error rate at said voltage slicing level exceeds said threshold wherein

decoding symbols on said link and determining said decoding error rate at said voltage slicing level, said decoding comprising operating on groups of bits of a fixed bit length, each group of bits comprising a target bit and bits adjacent in time to said target bit, said bits adjacent in time to said target bit being assumed to affect a voltage of said target bit before decoding due to inter-symbol interference.

13. The method of claim 12 wherein said determining said decoding error rate at said voltage slicing level utilises error correction bits in a received bit stream.

14. The method of claim 12 wherein said determining said decoding error rate at said voltage slicing level comprises receiving known test sequences and comparing said test sequences with corresponding decoded sequences.

15. The method of claim 12 further comprising deriving probability information from an assumed channel impulse response model, said probability information comprising a probability of occurrence for all possible groups of bits of said fixed bit length at each said voltage slicing level of said ADC.

16. The method of claim 15 wherein said probability information is used to decode said symbols.

Assignments (9)