LDMOS transistor with improved gate shield
View Patent ↗A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate.
1. A LDMOS transistor comprising:
a) a semiconductor substrate having a major surface,
b) a source region and a drain region formed in the major surface with a channel region therebetween,
c) a gate overlying the major surface and the channel region with a gate insulator between the gate and channel region,
d) a source contact including a plated metal electrically connected to the source region and a drain contact including plated metal electrically connected to the drain region, and
e) a metal gate shield overlying the gate and insulated therefrom, the gate shield extending to the source contact without the source contact plated metal overlying the gate, whereby the gate shield is thin relative to the thickness of the source contact and the drain contact and thereby reduces coupling capacitance between the gate shield and the drain contacts;
wherein a portion of the source contact that is thicker than the gate shield extends over the gate shield and over the sate insulator, and wherein the gate shield extends beneath the source contact to contact the source region, whereby the source contact is electrically connected to the source region through the gate shield.
2. The LDMOS transistor as defined in claim 1 wherein the shield comprises stacked metal layers including a top gold seed layer and an intermediate gold diffusion barrier layer.
3. The LDMOS transistor as defined in claim 2 wherein the shield comprises TiW—TiWN—TiW—Au.
4. The LDMOS transistor as defined in claim 2 wherein the substrate includes an epitaxial layer, the source region and the drain region being formed in a surface of the epitaxial layer.
5. The LDMOS transistor as defined by claim 4 and further including a highly doped sinker region ohmically connecting the source region to the substrate underlying the epitaxial layer.
6. The LDMOS transistor as defined by claim 4 wherein the substrate is P+ doped and the epitaxial layer is P− doped.
7. The LDMOS transistor as defined by claim 4 wherein the source contact and the drain contact are planarized by repeated plating of metal thereon.