IP Library Granted Patent US 7,493,620
Granted Patent B2
US 7,493,620 · App. 10/871,951 · Granted Feb 17, 2009

Transfer of waiting interrupts

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Quick Facts
Patent No.
US 7,493,620
App. No.
10/871,951
Granted
Feb 17, 2009
Kind
B2
Abstract

Apparatus and methods are provided for transferring interrupts. One embodiment of a computing device includes a first processor, a memory in communication with the first processor, and computer executable instructions stored in memory and executable on the first processor. The computer executable instructions are provided to select an interrupt, that has been waiting to be processed, for transfer from the first processor, check a number of other processors to select a second processor that has a short wait time for processing the interrupt, and transfer the interrupt from the first processor to the second processor.

Claims (41)

1. A computing device, comprising:

a first processor;

a memory in communication with the first processor; and

computer executable instructions stored in memory and executable on the first processor to:

select a first interrupt, that has been waiting to be processed, for transfer from the first processor based upon an expiration time of the first interrupt that has been passed by a current time of the first processor;

check a number of other processors in the computing device to select a second processor that has a wait time due to one or more interrupts already in a queue of the second processor, based on an evaluation that the wait time due to the one or more interrupts already in a queue of the second processor is less than a threshold wait time; and

transfer the first interrupt from the first processor to the second processor.

2. The computing device of claim 1 , wherein computer executable instructions for selecting the first interrupt are executable to select a timeout interrupt.

3. The computing device of claim 1 , wherein the number of other processors are provided on the computing device.

4. The computing device of claim 1 , wherein the first processor is provided on a first computing device and the number of other processors are provided on a number of other computing devices.

5. The computing device of claim 1 , wherein the selection of the second processor is based upon a wait time for a second interrupt on the second processor that is less than a threshold wait time.

6. A computing system, comprising:

a first processor;

a memory;

a second processor; and

computer executable instructions in the memory which are executable to:

identify a length of time a first interrupt has been waiting to be processed on the first processor;

compare the length of time the first interrupt has been waiting to a threshold time;

select the first interrupt for transfer, if the length of time the first interrupt has been waiting is equal to or greater than the threshold time, and therefore whether an expiration time for processing the first interrupt has expired based on a current time of the first processor;

check a number of other processors to select a second processor that has a wait time, due to one or more interrupts already in a queue of the second processor based on an evaluation that the wait time due to the one or more interrupts already in a queue of the second processor is less than the threshold time; and

transfer the processing of the first interrupt from the first processor to the second processor.

7. The computing system of claim 6 , wherein the computer executable instructions execute to select a set of interrupts for transfer based upon whether an expiration time for processing one of the interrupts of the set of interrupts has expired.

8. The computing system of claim 7 , wherein the computer executable instructions execute to transfer the set of interrupts to the second processor.

9. The computing system of claim 6 , wherein the computer executable instructions execute to select a set of chronologically organized interrupts for transfer based upon whether an earliest expiration time of an interrupt of the set of interrupts has expired.

10. The computing system of claim 9 , wherein the computer executable instructions execute to transfer the set of interrupts to the second processor.

11. The computing system of claim 9 , wherein the computer executable instructions execute to transfer the set of interrupts to the second processor and to one or more other processors.

12. A computer readable medium having instructions for causing a device to perform a method, comprising:

selecting a first interrupt, that has been waiting to be processed, for transfer from the first processor based upon whether an expiration time for processing the interrupt has expired based on a current time of the first processor;

checking a number of other processors to select a second processor that has a wait time due to one or more interrupts already in a queue of the second processor based on an evaluation that the wait time due to the one or more interrupts already in a queue of the second processor is less than a threshold wait time; and

transferring the first interrupt from the first processor to the second processor.

13. A method for handling interrupts, comprising:

identifying a length of time a first interrupt has been waiting to be processed on a first processor;

comparing the length of time the first interrupt has been waiting to a threshold time;

selecting the first interrupt for transfer, if the length of time the first interrupt has been waiting is equal to or greater than the threshold time;

selecting all interrupts that have been awaiting processing for a length of time longer than the first interrupt;

checking a number of other processors to select a second processor that has a wait time due to one or more interrupts already in a queue of the second processor based on an evaluation that the wait time due to the one or more interrupts already in a queue of the second processor is less than the threshold time; and

transferring the processing of the first interrupt from the first processor to the second processor.

14. The method of claim 13 , wherein transferring the processing of the first interrupt includes transferring all selected interrupts from the first processor to the second processor.

15. The method of claim 13 , wherein the first interrupt is represented by a kernel object and wherein transferring the processing of the first interrupt includes unlinking a kernel object representing the first interrupt from the first processor and linking the kernel object to the second processor.

16. The method of claim 13 , wherein selecting the processing of the first interrupt for transfer includes selecting all interrupts for transfer that are positioned in a queue after the first interrupt.

17. The method of claim 16 , wherein transferring the processing of the first interrupt includes transferring all selected interrupts from the first processor to the second processor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 057650/0537 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2004
From: PAREKH, HARSHADRAI G.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 015498/0673 →