One gate delay output noise insensitive latch
View Patent ↗A one gate delay output noise insensitive latch includes an input node, an output node, a storage node, a not storage node, and a data clock line. A primary latch element is connected to the input node, the output node, and the data clock line. A mirror primary latch element is connected to the input node in parallel with the primary latch element, to the storage node, and to the data clock line. A weak keeper is connected to the storage node and to the not storage node. A strong enabled tri-state keeper is connected to the not storage node, to the data clock line, and to the output node. The input node is either a dynamic data input node or a static data input node. Optionally, the weak keeper is also clock enabled.
1. A structure comprising:
a dynamic data input terminal;
a storage node;
a not storage node;
an output terminal;
a data clock line;
a staticizer connected to the input terminal, the output terminal, and the data clock line;
a mirror staticizer connected to the input terminal in parallel with the staticizer, to the storage node, and to the data clock line;
a weak keeper having an input terminal connected to the storage node and an output terminal connected to the not storage node; and
a strong enabled tri-state keeper connected to the not storage node, to the data clock line, and to the output terminal, wherein the strong enabled tri-state keeper comprises:
a transistor of a first type comprising:
a first lead couplable to and de-couplable from a first power supply voltage;
a second lead connected to the output terminal; and
a third lead connected to the data clock line;
a transistor of second type comprising a first lead connected to the output terminal;
a second lead couplable to and de-couplable from a second power supply voltage; and
a third lead connected to the not storage node;
another transistor of the first type comprising a first lead connected to the first power supply voltage;
a second lead connected to the first lead of the transistor of the first lead; and
a third lead connected to the not storage node;
wherein the another transistor is shared with the weak keeper.
2. The structure of claim 1 wherein the weak keeper is connected to the data clock line.
3. The structure of claim 1 wherein the weak keeper comprises a weak feedback inverter keeper.
4. The structure of claim 1 wherein the structure in included in a semi-dynamic flip-flop.
5. A structure comprising:
a dynamic data input terminal;
a storage node;
a not storage node;
an output terminal;
a data clock line;
a staticizer connected to the input terminal, the output terminal, and the data clock line;
a mirror staticizer connected to the input terminal in parallel with the staticizer, to the storage node, and to the data clock line;
a weak keeper having an input terminal connected to the storage node and an output terminal connected to the not storage node; and
a strong enabled tri-state keeper connected to the not storage node, to the data clock line, and to the output terminal, wherein the staticizer further comprises:
a transistor of a first type comprising:
a first lead connected to a first power supply voltage;
a second lead connected to the output terminal; and
a third lead connected to the dynamic data input terminal.
6. The structure of claim 5 wherein the staticizer further comprises:
a transistor of a second type comprising:
a first lead connected to the output terminal;
a second lead couplable to and de-couplable from a second power supply voltage; and
a third lead connected to the data clock line.
7. The structure of claim 6 wherein the staticizer further comprises;
another transistor of the second type comprising:
a first lead connected to the second power supply voltage;
a second lead connected to the second lead of the transistor of the second type; and
a third lead connected to the dynamic data input terminal.
8. The structure of claim 7 wherein the another transistor is shared with the mirror staticizer.