IP Library Granted Patent US 7,116,298
Granted Patent B2
US 7,116,298 · App. 10/874,357 · Granted Oct 3, 2006

Active matrix display device

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Quick Facts
Patent No.
US 7,116,298
App. No.
10/874,357
Granted
Oct 3, 2006
Kind
B2
Abstract

A display device includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

Claims (9)

1. A display device being provided with a display driving circuit including a dynamic shift register which includes a first MISTFT on a substrate surface, wherein:

the dynamic shift register is comprised of a second MISTFT and a third MISTFT which use polycrystalline silicon as a semiconductor layer:

the first MISTFT includes a gate electrode, a first electrode and a second electrode, wherein a voltage of the gate electrode is boosted by a voltage of the first electrode changing from low level to high level,

the second MISTFT is connected between a ground level line and the gate electrode of the first MISTFT, and

the third MISTFT is comprised such that the gate electrode of the first MISTFT is dropped to a ground level during a period other than a period in which a signal of high level is transmitted into the gate electrode of the first MISTFT.

2. A display device according to claim 1 ,

wherein the dynamic shift register includes a connection of a plurality of stages, each stage including the first MISTFT, the second MISTFT, and the third MISTFT, and wherein an output signal from a preceding stage of said plurality of stages is input into the third MISTFT of a next stage of said plurality of stages.

3. A display device according to claim 1 ,

wherein the dynamic shift register includes a connection of a plurality of stages, each stage including the first MISTFT, the second MISTFT, and the third MISTFT, wherein a first synchronous pulse is input into the first MISTFT of a preceding stage of said plurality of stages, and wherein a second synchronous pulse is input into the first MISTFT of a next stage of said plurality of stages.

Assignments (4)
COMPANY SPLIT PLAN TRANSFERRING FIFTY (50) PERCENT SHARE OF PATENTS AND PATENT APPLICATIONS Recorded Dec 12, 2011
From: HITACHI DISPLAYS, LTD.
To: IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027362/0466 →
COMPANY SPLIT PLAN TRANSFERRING ONE HUNDRED (100) PERCENT SHARE OF PATENT AND PATENT APPLICATIONS Recorded Dec 12, 2011
From: HITACHI, LTD.
To: HITACHI DISPLAYS, LTD.
Reel/Frame 027362/0612 →
MERGER/CHANGE OF NAME Recorded Dec 12, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027363/0315 →
MERGER Recorded Jun 23, 2011
From: HITACHI DEVICE ENGINEERING CO., LTD.
To: HITACHI DISPLAYS, LTD.
Reel/Frame 026481/0032 →