Method and system for reading instructions from NAND flash memory and writing them into SRAM for execution by a processing device

1. A method for efficient execution of code in memory by a processing device, the method comprising:

determining whether a first type of memory is present;

if said first type of memory is present, copying a loader image stored in said first type of memory to instruction memory;

executing said copied loader image to copy application code from said first type of memory to a second type of memory; and

executing said copied application code from said second type of memory, wherein said instruction memory, which stores said copied loader image, is separate from said first type of memory, which stores said loader image and said application code, and said second type of memory.

2. The method according to claim 1 , wherein said first type of memory is a NAND flash memory.

3. The method according to claim 1 , wherein said second type of memory is an SDRAM.

4. The method according to claim 1 , comprising jumping to entry of said loader image.

5. The method according to claim 1 , comprising copying vectors to an instruction memory.

6. The method according to claim 5 , comprising executing code for said loader image.

7. The method according to claim 1 , comprising copying vectors from said first type of memory to an instruction memory.

8. The method according to claim 7 , comprising mapping said copied vectors to a startup address.

9. The method according to claim 1 , comprising copying system parameters from said first type of memory to said second type of memory.

10. The method according to claim 1 , comprising jumping to start of said application code in said second type of memory.

11. The method according to claim 10 , comprising initiating said execution of said copied application code from a location where said jump to start of said application code is.

12. A machine-readable storage having stored thereon, a computer program having at least one code section for efficient execution of code in memory by a processing device, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

determining whether a first type of memory is present;

if said first type of memory is present, copying a loader image stored in said first type of memory to instruction memory;

executing said copied loader image to copy application code from said first type of memory to a second type of memory; and

executing said copied application code from said second type of memory, wherein said instruction memory, which stores said copied loader image, is separate from said first type of memory, which stores said loader image and said application code, and said second type of memory.

13. The machine-readable storage according to claim 12 , wherein said first type of memory is a NAND flash memory.

14. The machine-readable storage according to claim 12 , wherein said second type of memory is an SDRAM.

15. The machine-readable storage according to claim 12 , comprising code for jumping to entry of said loader image.

16. The machine-readable storage according to claim 12 , comprising code for copying vectors to an instruction memory.

17. The machine-readable storage according to claim 16 , comprising code for executing said loader image.

18. The machine-readable storage according to claim 12 , comprising code for copying vectors from said first type of memory to an instruction memory.

19. The machine-readable storage according to claim 18 , comprising code for mapping said copied vectors to a startup address.

20. The machine-readable storage according to claim 12 , comprising code for copying system parameters from said first type of memory to said second type of memory.

21. A system for efficient execution of code in memory by a processing device, the system comprising:

at least one processor that determines whether a first type of memory is present;

said at least one processor copies a loader image stored in said first type of memory to instruction memory, if said first type of memory is present;

said at least one processor executes said copied loader image to copy application code from said first type of memory to a second type of memory; and

said at least one processor executes said copied application code from said second type of memory, wherein said instruction memory, which stores said copied loader image, is separate from said first type of memory, which stores said loader image and said application code, and said second type of memory.

22. The system according to claim 21 , wherein said first type of memory is a NAND flash memory.

23. The system according to claim 21 , wherein said second type of memory is an SDRAM.

24. The system according to claim 21 , wherein said at least one processor jumps to entry of said loader image.

25. The system according to claim 21 , wherein said at least one processor copies vectors to an instruction memory.

26. The system according to claim 25 , wherein said at least one processor executes code for said loader image.

27. The system according to claim 21 , wherein said at least one processor copies vectors from said first type of memory to an instruction memory.

28. The system according to claim 27 , wherein said at least one processor maps said copied vectors to a startup address.

29. The system according to claim 21 , wherein said at least one processor copies system parameters from said first type of memory to said second type of memory.