Measure and recording of traffic parameters in data transmission networks
View Patent ↗The invention relates to a method and apparatus for measuring and recording traffic at nodes in a data transmission network. In particular the invention provides a method of accurately counting individual activities of traffic at individual nodes. The invention is carried out in hardware by using a counter or number of counters which count individual activities of traffic on a preset activity condition being sensed at a node. The invention has the advantage that accurate measurement of traffic at a node is achieved. The invention is also easy to implement in hardware and overcomes the problems inherent in present software solutions.
1. A sampling circuit for the measurement and recording of traffic parameters as system activity counts at a node in a data transmission network comprising:
a plurality of addressable registers forming a time counter and at least one system counter;
a multiplexor connected to each counter;
a global multiplexor connected to each per-counter multiplexor;
a control register connected to each multiplexor the control register being programmed to configure each node multiplexor to handle the bits at each counter in accordance with a pre-set count condition and to assert an inhibit and reset-signal for transmission to each counter on sensing the pre-set count condition;
the control register being programmed to configure the global multiplexor to combine the outputs of node multiplexors to assert the inhibit and re-set signal; and
circuit counting means for the individual system activity counts in real time.
2. A sampling circuit as claimed in claim 1 , in which the counters are combined in a counter assembly.
3. A sampling circuit as claimed in claim 1 , in which the counter assembly comprises a time counter, a system counter for counting bytes and a system counter for counting packets.
4. A sampling circuit for the measurement and recording of traffic parameters as system activity counts at a node in a data transmission network comprising:
a plurality of addressable registers forming a time counter and at least one system counter;
a multiplexor coupled to each counter;
a global multiplexor coupled to each per-counter multiplexor;
a control register coupled to each multiplexor, the control register being programmed to configure each node multiplexor to handle the bits at each counter in accordance with a pre-set count condition and to assert an inhibit and reset-signal for transmission to each counter on sensing the pre-set count condition, the control register being programmed to configure the global multiplexor to combine the outputs of node multiplexors to assert the inhibit and re-set signal; and
a circuit counter for maintaining the individual system activity counts in real time.
5. A sampling circuit as claimed in claim 4 , wherein the sampling circuit further comprises a counter assembly including a combination of a time counter, a system counter for counting bytes and a system counter for counting packets.
6. A sampling circuit for the measurement and recording of traffic parameters as system activity counts at a node in a data transmission network comprising:
a plurality of addressable registers forming a time counter and at least one system counter;
a plurality of node multiplexors, each node multiplexor coupled to one of the at least one system counter and/or the time counter;
a global multiplexor coupled to the plurality of node multiplexors;
a control register coupled to the global multiplexor and to each of the plurality of node multiplexors, the control register being programmed to
configure each node multiplexor to handle the bits at each counter in accordance with a count condition, and
configure the global multiplexor to combine the outputs of node multiplexors to assert an inhibit and reset-signal for transmission to each counter upon sensing the count condition; and
a circuit counter for counting the individual system activity counts in real time.
7. A sampling circuit as claimed in claim 6 , wherein the counters are combined in a counter assembly.
8. A sampling circuit as claimed in claim 7 , wherein the counter assembly comprises a combination of a time counter, a system counter for counting bytes and/or a system counter for counting packets.