Method for manufacturing semiconductor device
View Patent ↗Several a transistor, which are inhibited short channel effect moderately according to each transistor's channel length, are formed on a same SOI substrate. In the present invention, forming a first transistor on SOI substrate, and forming a second transistor which has a gate electrode whose length is longer than a gate length of the first transistor in a channel direction The impurities are doped from above a surface of the SOI substrate in an oblique direction against the surface, and from source side and drain side of the first transistor and the second transistor. By this means, a pocket layer is formed under an insulator layer of a SOI substrate.
1. A method for manufacturing a semiconductor device, said method comprising;
providing a substrate which has a semiconductor layer and an insulating layer, wherein the insulating layer is laid on the substrate and the semiconductor layer is laid on the insulating layer;
forming a first transistor at the semiconductor layer;
forming a second transistor at the semiconductor layer, wherein the second transistor has a gate electrode whose length is longer than a gate length of the first transistor in a channel direction; and
doping impurities into the substrate under the insulator layer, using the gate electrodes of the first and second transistors as masks;
wherein the impurities are doped from above a surface of the semiconductor layer in an oblique direction against the surface, and from source side and drain side of the first transistor and the second transistor; and
wherein the impurities are doped so that a region of the substrate into which the impurities are doped from the source side of the first transistor overlaps a region of the substrate into which the impurities are doped from the drain side of the first transistor.
2. The method as claimed in claim 1 , wherein the first transistor is used for a memory circuit and the second transistor is used for a logic circuit.
3. The method as claimed in claim 1 , wherein the first transistor is used for a digital circuit and the second transistor is used for an analog circuit.
4. The method as claimed in claim 1 , wherein the first transistor is used for a core circuit and the second transistor is used for a peripheral circuit.
5. The method as claimed in claim 1 , wherein the impurities doped from above do not overlap under the gate of the second transistor.
6. The method as claimed in claim 1 , wherein the impurities are doped so that a region of the substrate into which the impurities from the source side of the second transistor are doped is positioned away from a region of the substrate into which the impurities from the drain side of the second transistor are doped.
7. A method for manufacturing semiconductor device, said method comprising;
providing a substrate which has a semiconductor layer and an insulating layer, wherein the insulating layer is laid on the substrate and the semiconductor layer is laid on the insulating layer;
forming a first transistor on the semiconductor layer;
forming a second transistor on the semiconductor layer, wherein the second transistor has a gate electrode whose length is longer than a gate length of the first transistor in a channel direction;
doping impurities into the substrate under the insulator layer, using the gate electrodes of the first and second transistors as masks;
wherein the impurities are doped from source and drain sides of the first and second transistors, and so as to be right under the gate electrodes of the first and second transistors; and
wherein the impurities are doped so that a region of the substrate into which the impurities are doped from the source side of the first transistor overlaps a region of the substrate into which the impurities are doped from the drain side of the first transistor.
8. The method as claimed in claim 7 , wherein the impurities are doped into one region of the substrate from both the source side and the drain side of the first transistor.
9. The method as claimed in claim 6 , wherein the first transistor is used for a memory circuit and the second transistor is used for a logic circuit.
10. The method as claimed in claim 7 , wherein the first transistor is used for a digital circuit and the second transistor is used for an analog circuit.
11. The method as claimed in claim 7 , wherein the first transistor is used for a core circuit and the second transistor is used for a peripheral circuit.
12. The method as claimed in claim 7 , wherein the impurities doped from above do not overlap under the gate of the second transistor.
13. The method as claimed in claim 7 , wherein the impurities are doped so that a region of the substrate into which the impurities from the source side of the second transistor are doped is positioned away from a region of the substrate into which the impurities from the drain side of the second transistor are doped.