IP Library Granted Patent US 7,596,699
Granted Patent B2
US 7,596,699 · App. 10/875,706 · Granted Sep 29, 2009

Battery authentication system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,596,699
App. No.
10/875,706
Granted
Sep 29, 2009
Kind
B2
Abstract

An authentication process for authenticating a battery to a cellular telephone includes the step of receiving a challenge from the cellular telephone at the battery over a single wire conductor. In response to the challenge, the seed values are retrieved from the memory and a response is generated based upon the challenge and the seed values. The response is transmitted back to the cellular telephone from the battery over the single conductor so that a comparison with a similar response generated by the cellular telephone may be made.

Claims (43)

1. An authentication system, comprising:

a first device comprising:

a first device input/output interface for communicating with a connected battery;

a first device response generator for generating a first challenge response responsive to a challenge received over the first device input/output interface and locally stored seed values, the first device response generator comprising:

a first plurality of multiplexers, each multiplexer of the first plurality of multiplexers connecting one of a plurality of inputs of the multiplexer to an output of the multiplexer responsive to a first stored address code, each of the first plurality of multiplexers having an input of the plurality of inputs connected to receive the first challenge response;

a first plurality of hash function calculators each having an input connected to one of the plurality of multiplexers and a first output and a second output, the first output of each of the first plurality of hash function calculators connected to at least two of the plurality of inputs of the first plurality of multiplexers, each of the first plurality of hash function calculators generating an output bit on each of the first output of the first plurality of hash function calculations and the second output of the first plurality of hash function calculations responsive to the challenge and the locally stored seed values;

a first logic circuit connected to each of the second outputs of the first plurality of hash function calculators for combining the outputs of each of the first plurality of hash function calculators into the first challenge response;

a first memory for storing the seed values and the address codes;

a connected battery comprising:

a second device input/output interface for communicating with the first device;

a second device response generator for generating a challenge response responsive to a challenge received over the second device input/output interface and locally stored seed values, the second device response generator comprising:

a second plurality of multiplexers, each multiplexer of the second plurality of multiplexers connecting one of a plurality of inputs of the multiplexer to an output of the multiplexer responsive to a stored address code, each of the second plurality of multiplexers having an input of the plurality of inputs connected to receive the second challenge response;

a second plurality of hash function calculators each having an input connected to one of the second plurality of multiplexers and a first output and a second output, the first output of each of the second plurality of hash function calculators connected to at least two of the plurality of inputs of the second plurality of multiplexers, each of the second plurality of hash function calculators generating an output bit on each of the first output of the second plurality of hash function calculators and the second output of the second plurality of hash function calculators responsive to the challenge and the locally stored seed values;

a second logic circuit connected to each of the second outputs of the second plurality of hash function calculators for combining the outputs of each of the second plurality of hash function calculators into the second challenge response;

a second memory for storing the seed values and the address codes; and

wherein the first device compares the first challenge response with the second challenge response to determine whether to authenticate the connected battery.

2. The authentication system of claim 1 , wherein the first and second logic circuits comprise an exclusive OR circuit.

3. The authentication system of claim 1 , wherein the plurality of hash function calculators comprise a plurality of cyclic redundancy check (CRC) calculators.

4. The authentication system of claim 3 , wherein the cyclic redundancy check (CRC) calculators are implemented in a shift register.

5. An authentication system for authenticating a battery to an associated electronic device, comprising:

a device input/output interface for communicating with the associated electronic device;

a device response generator for generating a challenge response responsive to a challenge received over the interface and locally stored seed values, the device response generator comprising:

a plurality of multiplexers, each multiplexer of the plurality of multiplexers connecting one of a plurality of inputs to the multiplexer to an output of the multiplexer responsive to a stored address code, each of the plurality of multiplexers having an input of the plurality of inputs connected to receive the challenge response;

a plurality of hash function calculators each having an input connected to one of the plurality of multiplexers and a first output and a second output, the first output of each of the plurality of hash function calculators connected to at least two of the plurality of inputs of the plurality of multiplexers, each of the plurality of hash function calculators generating an output bit on each of the first output and the second output responsive to the challenge and the locally stored seed values;

a logic circuit connected to each of the second outputs of the plurality of hash function calculators for combining the outputs of each of the plurality of hash function calculators into the challenge response;

a memory for storing the seed values and the address codes.

6. The authentication system of claim 5 , wherein the logic circuit comprises an exclusive OR circuit.

7. The authentication system of claim 5 , wherein the plurality of hash function calculators comprise a plurality of cyclic redundancy check (CRC) calculators.

8. The authentication system of claim 5 , wherein said device response generator performs a hash function on the challenge to generate a hash code.

9. The authentication system of claim 6 , wherein said seed values include a polynomial code.

10. The authentication system of claim 6 , wherein said seed values include initial register values.

11. A method for authenticating a battery to an associated electronic device, comprising:

receiving a challenge at the battery from the associated electronic device;

multiplexing the challenge with outputs from a plurality of hash function processes to generate a plurality of multiplexed data streams, wherein the challenge is multiplexed with the outputs from the plurality of hash function processes responsive to a stored address code;

performing hash function calculations on each of the multiplexed data streams responsive to locally stored seed values and the challenge to generate a first output and a second output—for each of the multiplexed data streams;

providing the first output to be multiplexed into at least two of the multiplexed data streams;

combining the second outputs from each of the hash function calculations using a logic function to create a first challenge response, wherein the step of combining further comprise the step of exclusive ORing the second outputs from each of the hash function calculations;

forwarding the first challenge response from the battery to the associated electronic device.

12. The method of claim 11 , further including the steps of:

comparing the first challenge response and a second challenge response generated at the associated electronic device; and

determining whether to authenticate the battery responsive to the comparison.

13. The method of claim 11 , wherein the steps of performing hash function calculations further comprise the step of performing cyclic redundancy check (CRC) calculations.

14. The method of claim 11 , wherein the step of performing CRC calculations further comprises the step of performing cyclic redundancy check (CRC) calculations using a shift register.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE PREVIOUSLY RECORDED ON REEL 015518 FRAME 0557. ASSIGNOR(S) HEREBY CONFIRMS THE NAME OF ASSIGNEE WAS RECORDED INCORRECTLY AS INTERSIL AMERICAS, INC. AND SHOULD HAVE BEEN RECORDED AS INTERSIL AMERICAS INC.. Recorded Jul 22, 2014
From: KWOK, CHUNG Y.
To: INTERSIL AMERICAS INC.
Reel/Frame 033379/0839 →
CHANGE OF NAME Recorded Jul 22, 2014
From: INTERSIL AMERICAS INC.
To: INTERSIL AMERICAS LLC
Reel/Frame 033380/0140 →
SECURITY AGREEMENT Recorded Apr 30, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.; ZILKER LABS, INC.; KENET, INC.; INTERSIL AMERICAS INC.; ELANTEC SEMICONDUCTOR, INC.; D2AUDIO CORPORATION; PLANET ATE, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024320/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2004
From: KWOK, CHUNG Y.
To: INTERSIL AMERICAS, INC.
Reel/Frame 015518/0557 →