IP Library Granted Patent US 7,019,508
Granted Patent B2
US 7,019,508 · App. 10/875,819 · Granted Mar 28, 2006

Temperature compensated bias network

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Quick Facts
Patent No.
US 7,019,508
App. No.
10/875,819
Granted
Mar 28, 2006
Kind
B2
Abstract

A method and apparatus for a temperature compensated bias network, such as may be embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of desired temperature characteristics with good stability. Current mirror components with active leakage circuits may act to provide consistent operating parameters over a wide range of temperatures. Improved compensation and linearity may be provided using features disclosed.

Claims (42)

1. A circuit for providing a temperature compensated current comprising:

a input transistor having an input transistor control terminal and having an input transistor current terminal passing a reference current;

a first buffer transistor having a first buffer transistor control terminal operable to receive a buffer control voltage proportional to the reference current and further having a first buffer transistor current terminal operable to pass a first leakage current;

a first leakage block comprising a temperature dependent block operable to pass the first leakage current;

a second buffer transistor having a second buffer transistor control terminal operable to receive the buffer control voltage and further having a second buffer transistor current terminal operable to pass a second leakage current;

a second leakage block operable to pass the second leakage current; and

an output transistor operable to generate an output current proportional to the reference current and further proportional to a ratio of the first and second leakage currents.

2. The circuit of claim 1 wherein:

the second leakage block consists of an ohmic resistance.

3. The circuit of claim 1 wherein:

the second leakage block comprises a diode.

4. The circuit of claim 3 wherein:

the second leakage block further comprises an ohmic resistance.

5. The circuit of claim 1 wherein

the temperature dependent block comprises a current mirror and an offset linearizing resistor.

6. A circuit for providing a temperature compensated current comprising:

a input transistor having an input transistor control terminal and having an input transistor current terminal passing a reference current;

a first buffer transistor having a first buffer transistor control terminal operable to receive a buffer control voltage proportional to the reference current and further having a first buffer transistor current terminal operable to pass a first leakage current;

a first leakage block operable to pass the first leakage current;

a second buffer transistor having a second buffer transistor control terminal operable to receive the buffer control voltage and further having a second buffer transistor current terminal operable to pass a second leakage current;

a second leakage block comprising a temperature dependent block operable to pass the second leakage current; and

an output transistor operable to generate an output current proportional to the reference current and further proportional to a ratio of the first and second leakage currents.

7. The circuit of claim 6 wherein:

the first leakage block consists of an ohmic resistance.

8. The circuit of claim 6 wherein:

the first leakage block comprises a diode.

9. The circuit of claim 8 wherein:

the first leakage block further comprises an ohmic resistance.

10. The circuit of claim 6 wherein

the temperature dependent block comprises a current mirror and an offset linearizing resistor.

11. A method for providing a temperature compensated current comprising the acts of:

mirroring a proportion of a reference current using an input transistor having an input transistor control terminal passing a control current and further using an output transistor;

providing an input buffer transistor and an output buffer transistor;

ratioing a temperature dependent leakage current of the input buffer transistor with a leakage current of the output buffer transistor; and

generating an output current proportional to the reference current and further proportional to the ratioing

whereby the circuit operates to produce a current with temperature compensation.

12. A method for providing a temperature compensated current comprising the acts of:

mirroring a proportion of a reference current using an input transistor having an input transistor control terminal passing a control current and further using an output transistor;

providing an input buffer transistor and an output buffer transistor;

ratioing a leakage current of the input buffer transistor with a temperature dependent leakage current of the output buffer transistor; and

generating an output current proportional to the reference current and further proportional to the ratioing

whereby the circuit operates to produce a current with temperature compensation.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2017
From: II-VI OPTOELECTRONIC DEVICES, INC.
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 042551/0708 →
CHANGE OF NAME Recorded May 1, 2017
From: ANADIGICS, INC.
To: II-VI OPTOELECTRONIC DEVICES, INC.
Reel/Frame 042381/0761 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS NUMBER 6790900 AND REPLACE IT WITH 6760900 PREVIOUSLY RECORDED ON REEL 034056 FRAME 0641. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Nov 21, 2016
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 040660/0967 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 037973 FRAME: 0226. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded May 18, 2016
From: ANADIGICS, INC.
To: II-VI INCORPORATED
Reel/Frame 038744/0835 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2016
From: II-VI INCORPORATED
To: ANADIGICS, INC.
Reel/Frame 038119/0312 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Mar 1, 2016
From: ANADIGICS, INC.
To: II-IV INCORPORATED
Reel/Frame 037973/0226 →
RELEASE OF SECURITY INTEREST Recorded Mar 1, 2016
From: SILICON VALLEY BANK
To: ANADIGICS, INC.
Reel/Frame 037973/0133 →
SECURITY AGREEMENT Recorded Oct 27, 2014
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 034056/0641 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2009
From: RATEGH, HAMID REZA; HOZOURI, BEHZAD TAVASSOLI
To: ANADIGICS, INC.
Reel/Frame 022449/0949 →