Dual port SRAM cell

1. A dual port SRAM cell comprising:

a writing section having a transistor for inputting a data input signal from a bit line in response to a control signal from a word line;

a data storage section having only three transistors for storing the data input signal from the outside through the writing section; and

a reading section having two transistors for reading the data input signal stored in the data storage section in response to control signal from a common line.

2. The dual port SRAM cell as recited in claim 1 , wherein a gate of a first transistor coupled to the word line, one port of the first transistor is connected to a single bit line and another port of the first transistor is coupled to a transistor that is coupled to the data storage section.

3. The dual port SRAM cell as recited in claim 2 , wherein the data storage section includes:

a second transistor whose gate is coupled to a first node on said another port of the first transistor, and drain and source are connected to a first supply voltage and a second node, respectively;

a third transistor whose gate is connected to the second node, and drain and source are coupled to the first node and a second supply voltage, respectively; and

a fourth transistor whose gate is connected to the first node, and drain and source are coupled to the second node and the second supply voltage, respectively.

4. The dual port SRAM cell as recited in claim 3 , wherein the reading section includes:

a fifth transistor whose gate is coupled to the second node, and drain and source are connected to a third node and the second supply voltage, respectively; and

a sixth transistor whose gate is connected to a common line, and drain and source are coupled to a data line carrying data to be read, and the third node, respectively.

5. The dual port SRAM cell as recited in claim 4 , wherein the first, third, fourth, fifth and sixth transistors are NMOS transistors, and the second transistor is PMOS transistor.

6. The dual port SRAM cell as recited in claim 4 , wherein the data line is pulled-up to a high logic voltage level before the signal is outputted.

7. A dual port SRAM cell, comprising:

a writing section having a first transistor for inputting a data input signal from a bit line in response to a control signal from a word line;

a data storage section having only a second, a third and a fourth transistors, wherein the second transistor is coupled to the output port of the first transistor, the third transistor is operated inversely to the second transistor, and the fourth transistor is operated inversely to the third transistor, the output port of the first transistor, the input port of the second transistor, the gate of the third transistor and the gate of the fourth transistor being commonly coupled to a first node and the input port of the third transistor and the output port of the fourth being commonly connected to a second node that is operated to have an inverse signal level to a signal level at the first node; and

a reading section having a fifth and a sixth transistors, wherein the fifth transistor whose gate is coupled to the second node is pull-down operated and the sixth transistor whose gate is operated by a common line is connected to the fifth transistor to form a third node, to output an inverse signal to the signal at the second node in response to the signal from the common line.

8. The dual port SRAM cell as recited in claim 7 , wherein the first, third, forth, fifth and sixth transistors are NMOS transistors, and the second transistor is PMOS transistor.

9. The dual port SRAM cell as recited in claim 7 , wherein the output port of the sixth transistor is pulled-up to a high logic voltage level by a pull-up transistor before a signal is outputted.

10. The dual port SRAM cell as recited in claim 7 , wherein the output port of the sixth transistor is pulled-up in H level by a pull-up transistor before a signal is outputted.

11. A dual port SRAM cell, comprising:

a first node at which data from a bit line is maintained, wherein the data is inputted from the bit line in response to a control signal from a word line, stored and outputted onto a data line in response to a signal from a common line;

a second node at which signal level is maintained in an inverse state to the input data at the first node; and

a third node at which a same signal level as maintained at the first node is outputted in response to the signal on the common line.

12. The dual port SRAM cell as recited in claim 11 , wherein the first node is commonly coupled to the output port of the first transistor, a gate of a second transistor, a gate of the third transistor, and a gate of a fourth transistor, for inputting the signal from the bit line in response to the input signal via the word line, and

the second node is commonly connected to the gate of the second transistor, the one port of the third transistor, the output port of the fourth transistor, and the gate of the fifth transistor.

13. The dual port SRAM cell as recited in claim 12 , wherein the first, third, forth and fifth transistors are NMOS transistors, and the second transistor is PMOS transistor.

14. The dual port SRAM cell as recited in claim 13 , wherein the third node is commonly connected to the fifth transistor and the sixth transistor whose gate is operated by the signal on the common line.

15. The dual port SRAM cell as recited in claim 14 , wherein the sixth transistor is NMOS transistor and its output port is pulled-up to a high logic voltage level by a pull-up transistor before a signal is outputted.

16. The dual port SRAM cell as recited in claim 11 , wherein the third node is commonly connected to the fifth transistor and the sixth transistor whose gate is operated by the signal on the common line.

17. The dual port SRAM cell as recited in claim 16 , wherein the sixth transistor is NMOS transistor and its output port is pulled-up to a high logic voltage level by a pull-up transistor before a signal is outputted.

18. The dual port SRAM cell as recited in claim 12 , wherein the third node is commonly connected to the fifth transistor and the sixth transistor whose gate is operated by the signal on the common line.

19. The dual port SRAM cell as recited in claim 18 , wherein the sixth transistor is NMOS transistor and its output port is pulled-up to a high logic voltage level by a pull-up transistor before a signal is outputted.