Unified memory controller
View Patent ↗A unified memory controller (UMC) is disclosed. The UMC may be used in a digital television (DTV) receiver. The UMC allows the DTV receiver to use a unified memory. The UMC accepts memory requests from various clients, and determines which requests should receive priority access to the unified memory.
1. A unified memory controller (UMC) comprising:
a page scheduler to schedule access requests for a memory;
a high-bandwidth client request scheduler coupled to the page scheduler to schedule high-bandwidth requests from high-bandwidth clients;
a low-latency scheduler coupled to the page scheduler to schedule low-latency requests from low-latency clients; and
an address translator coupled between the high-bandwidth client request scheduler and the page scheduler to translate two-dimensional requests from the high-bandwidth client request scheduler into one-dimensional requests.
2. The UMC of claim 1 , wherein the page scheduler comprises a first page scheduler to control a first memory rank and a second page scheduler to control a second memory rank.
3. The UMC of claim 1 , wherein the high-bandwidth client request scheduler arbitrates requests from high-bandwidth real time clients and from high-bandwidth batch clients.
4. The UMC of claim 3 , wherein the high-bandwidth real time clients are given priority over the high-bandwidth batch clients.
5. The UMC of claim 3 , wherein:
high-bandwidth real time clients need continuous and timely memory access; and
high-bandwidth batch clients consumes memory access not used by the high-bandwidth real time clients.
6. The UMC of claim 1 , wherein the memory is a unified memory to serve the high-bandwidth and the low-latency clients.
7. The UMC of claim 1 , wherein the page scheduler comprises:
a page scheduling unit;
a bank buffer coupled to the page scheduling unit; and
an interrupt buffer coupled to the page scheduling unit.
8. The UMC of claim 7 , wherein the bank buffer stores requests made by the high-bandwidth clients.
9. The UMC of claim 8 , wherein the bank buffer comprises a plurality of buffers corresponding to a plurality of memory banks.
10. The UMC of claim 9 , further comprising a least recently used (LRU) unit coupled to the page scheduling unit, to determine which of the plurality of bank buffers was least recently used.
11. The UMC of claim 7 , wherein the interrupt buffer stores requests made by the low-latency clients, and interrupts the page scheduler to fulfill the low latency request.
12. The UMC of claim 1 , wherein the high-bandwidth client request scheduler and the low-latency scheduler comprise a first level of arbitration, and wherein the page scheduler comprises a second level of arbitration.
13. The UMC of claim 1 , wherein the page scheduler is simplified and the high-bandwidth client request scheduler and the low-latency scheduler handle request ordering.
14. A method for ordering memory access requests to a unified memory comprising:
receiving high-bandwidth memory access requests and low-latency memory access requests;
arbitrating the high-bandwidth memory access requests to determine an order for fulfilling the high-bandwidth requests, including
determining a request type of each of the high-bandwidth requests,
sorting the high-bandwidth requests into a plurality of competition trees based on the request types of the high-bandwidth requests, and
determining a winning request for each of the competition trees;
wherein said sorting the high-bandwidth requests into a plurality of competition trees comprises
sorting real-time read requests into a first competition tree,
sorting real-time write requests into a second competition tree,
sorting batch read requests into a third competition tree, and
sorting batch write requests into a fourth competition tree;
fulfilling the low-latency requests; and
fulfilling the high-bandwidth requests in the order arbitrated after fulfilling the low-latency requests.
15. The method of claim 14 , wherein fulfilling the low-latency requests comprises:
assigning a priority order to the low-latency requests; and
fulfilling the low-latency requests according to the priority order.
16. The method of claim 15 , wherein assigning a priority order comprises:
determining a priority number for each low-latency request.
17. The method of claim 16 , wherein determining a priority number comprises:
determining a binary number comprising several fields, wherein each of the fields is set to signify an event.
18. The method of claim 15 , wherein assigning a priority order comprises:
assigning a programmable priority value to each low-latency request; and
increasing the programmable priority value as the request ages.
19. The method of claim 15 , further comprising:
scheduling the requests based on the priority, and delaying the requests so that the requests are scheduled just-in-time.
20. The method of claim 14 , further comprising:
interrupting the fulfilling of the low-latency requests, wherein the fulfilling of the low-latency requests fulfilling a queue of the low-latency requests; and
fulfilling the high-bandwidth requests before fulfilling the low-latency requests when high-bandwidth clients making the high-bandwidth requests are starved.
21. The method of claim 14 , wherein fulfilling the low-latency requests comprises:
interrupting the fulfilling the high-bandwidth requests.
22. The method of claim 21 , wherein interrupting the fulfilling of the high-bandwidth requests comprises waiting until a current request is fulfilled if an interrupting request is attempting to access a same memory bank as the current request.
23. A processing system comprising:
a random access memory (RAM);
a unified memory controller (UMC) coupled to the RAM to control access to the RAM, wherein the UMC includes
a page scheduler to issue requests to the RAM,
a high-bandwidth client request scheduler coupled to the page scheduler to handle high-bandwidth memory access requests from one or more high-bandwidth clients,
a low-latency scheduler coupled to the page scheduler to handle low-latency memory access requests from one or more low-latency clients, and
an address translator coupled between the high-bandwidth client request scheduler and the page scheduler to translate two-dimensional requests from the high-bandwidth client request scheduler into one-dimensional requests;
a low-latency client coupled to the UMC to use the RAM; and
a high-bandwidth client coupled to the UMC to use the RAM, wherein the low-latency client and the high-bandwidth client share the RAM.
24. The processing system of claim 23 , wherein the low-latency clients comprise a central processing unit (CPU), a peripheral control interface (PCI), input/output (I/O) peripherals, and an audio digital signal processor (DSP).
25. The processing system of claim 23 , wherein the page scheduler comprises a first page scheduler to control a first memory rank and a second page scheduler to control a second memory rank.
26. The processing system of claim 23 , wherein the high-bandwidth client request scheduler is configured to arbitrate memory access requests from high-bandwidth real time clients and from high-bandwidth batch clients, wherein the high-bandwidth real time clients are given priority over the high-bandwidth batch clients.