Liquid crystal display and thin film transistor array panel therefor
View Patent ↗A thin film transistor array panel is provided, which includes: a substrate; a plurality of first signal lines formed on the substrate; a plurality of second lines formed on the substrate, intersecting the first signal line, and including a plurality of curved portions having at least two curve points and a plurality of intermediate portions, the curved portions and the intermediate portions alternately connected; a plurality of pixel electrodes located substantially in areas defined by the first and the second signal lines; and a plurality of thin film transistors connected to the first and the second signal lines and the pixel electrodes.
1. A thin film transistor array panel comprising:
a substrate;
a plurality of first signal lines formed on the substrate;
a plurality of second signal lines formed on the substrate, intersecting the first signal lines, and including a plurality of bend portions having at least two zigzags and a plurality of straight potions, the bend portions and the straight portions alternating in series,
a plurality of pixel electrodes occupying a majority portion of areas defined by the first and the second signal lines; and
a plurality of thin film transistors connected to the first and the second signal lines and the pixel electrodes.
2. The thin film transistor array panel of claim 1 , wherein each of the bend portions of the second signal lines comprises a plurality of rectilinear portions connected to each other and making angles of about 45 degrees with the first signal lines in clockwise and counterclockwise manners, respectively.
3. The thin film transistor array panel of claim 1 , further comprising a plurality of third signal lines formed on the substrate, extending substantially parallel to the first signal lines, and overlapping the pixel electrodes to form storage capacitors.
4. The thin film transistor array panel of claim 1 , wherein the thin film transistors include terminal electrodes connected to the straight portions of the second signal lines.
5. The thin film transistor array panel of claim 1 , wherein the pixel electrodes have a cutout bisecting a corresponding of the pixel electrodes into two partitions.
6. A thin film transistor array panel comprising:
a substrate;
a plurality of first signal lines formed on the substrate;
a plurality of second signal lines formed on the substrate, intersecting the first signal lines, and including a plurality of bend portions having at least two zigzags and a plurality of straight portions, the bend portions and the straight portions alternating in series,
a plurality of pixel electrodes located substantially in areas defined by the first and the second signal lines; and
a plurality of thin film transistors connected to the first and the second signal lines and the pixel electrodes,
wherein the pixel electrodes have cutouts disposed on the data lines, each cutout bisecting a corresponding of the pixel electrodes into two partitions.
7. The thin film transistor array panel of claim 3 , wherein the third signal line comprises a plurality of projections having a shape of a chevron that is symmetrical with respect to the third signal line.
8. The thin film transistor array panel of claim 5 , wherein the cutout has a plurality of oblique portions expending substantially parallel to the bend portions of the second signal line.