Method of manufactuing inductor in semiconductor device
The present invention related to a method of manufacturing an inductor in a semiconductor device. A wire for an inductor is thickly formed by performing at least two damascene process in the same pattern of different patterns, thus reducing resistance and obtain a good Q (Quality) factor. Therefore, the present invention has effects that it can improve reliability of a process and electrical properties of a device.
1 . A method of manufacturing an inductor in a semiconductor device, comprising:
a first step of forming an interlayer insulating film on a semiconductor substrate;
a second step of forming a damascene pattern in the interlayer insulating film; and
a third step of forming a metal wire within the damascene pattern,
wherein the first to third steps are repeatedly performed to form wires that are vertically connected with no change in a width and have an increased thickness.
2 . The method as claimed in claim 1 , wherein the metal wire is formed using copper.
3 . The method as claimed in claim 1 , wherein the step of forming the metal wire comprises the steps of:
forming a barrier metal layer on the whole structure including the damascene pattern;
forming a metal seed layer on the whole structure including the damascene pattern; and
forming a metal wire within the damascene pattern by means of an electroplating method.
4 . The method as claimed in claim 1 , wherein the step of forming the metal wire comprises the steps of:
forming a barrier metal layer on the whole structure including the damascene pattern;
forming a metal seed layer on the whole structure including the damascene pattern;
stripping the metal seed layer on the interlayer insulating film, thus leaving the metal seed layer remained only within the damascene pattern; and
forming a metal wire within the damascene pattern by means of an electroplating method.
5 . The method as claimed in claim 1 , wherein the step of forming the metal wire comprises the steps of:
forming a barrier metal layer on the whole structure including the damascene pattern;
forming a metal seed layer on the whole structure including the damascene pattern;
stripping the metal seed layer and the barrier metal layer on the interlayer insulating film, thus leaving the barrier metal layer and the metal seed layer remained only within the damascene pattern; and
forming a metal wire within the damascene pattern by means of an electroplating method.
6 . The method as claimed in claim 5 , wherein the barrier metal layer is formed by means of atomic layer deposition.
7 . The method as claimed in claim 5 , further comprising the step of after the barrier metal layer is formed, stripping the barrier metal layer at the bottom of the damascene pattern.
8 . The method as claimed in claim 7 , wherein the barrier metal layer at the bottom of the damascene pattern is stripped in a PVD reactor in a RF etch mode, or in a RIE reactor or MERIE reactor by an anistropic etch process.
9 . The method as claimed in claim 5 , further comprising the step of after the metal wire is formed, performing an annealing process.
10 . The method as claimed in claim 9 , wherein the annealing process is performed in a furnace and is performed in a N 2 /H 2 atmosphere at a temperature of 100° C. to 200° C. for 30 minutes to 3 hours.