IP Library Granted Patent US 7,619,249
Granted Patent B2
US 7,619,249 · App. 10/878,529 · Granted Nov 17, 2009

Thin film array panel and manufacturing method thereof

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Quick Facts
Patent No.
US 7,619,249
App. No.
10/878,529
Granted
Nov 17, 2009
Kind
B2
Abstract

A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer; forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.

Claims (48)

1. A thin film array panel comprising:

a substrate;

a gate conductor formed on the substrate and including a gate electrode;

a gate insulating layer formed on the gate conductor;

a semiconductor layer formed on the gate insulating layer;

a data conductor including a source electrode and a drain electrode formed on at least a portion of the semiconductor layer;

an oxide film formed on the data conductor and having the same pattern as the data conductor;

a pixel electrode connected to the drain electrode; and

a passivation layer disposed between the data conductor and the pixel electrode, wherein the passivation layer is disposed on the oxide film, and wherein the oxide film is formed between the data conductor and the passivation layer.

2. The thin film array panel of claim 1 , wherein the data conductor comprises a Molybdenum containing metal film.

3. The thin film array panel of claim 2 , wherein the data conductor further comprises an Al containing metal film.

4. The thin film array panel of claim 1 , wherein the data conductor comprises a pair of Mo containing metal films and a Al containing metal film interposed between the Mo containing films.

5. The thin film array panel of claim 1 , wherein the semiconductor layer has substantially the same planar shape as the data conductor except for a portion between the source electrode and the drain electrode.

6. The thin film array panel of claim 1 , wherein the oxide film has a thickness of about 10-20 Å.

7. The thin film array panel of claim 2 , wherein the Mo containing metal film is oxidized to form the oxide film.

8. The thin film array panel of claim 4 , wherein one of the pair Mo containing metal films is oxidized to form the oxide film.

9. A thin film array panel comprising:

a substrate;

a gate conductor formed on the substrate and including a gate electrode;

a gate insulating layer formed on the gate conductor;

a semiconductor layer formed on the gate insulating layer;

a data conductor including an Mo containing metal film formed on at least a portion of the semiconductor layer;

a Molybdenum oxide film formed on the data conductor;

a passivation layer disposed on the Molybdenum oxide film; and

a pixel electrode connected to at least a portion of the data conductor.

10. A thin film array panel comprising:

a substrate;

a gate conductor formed on the substrate and including a gate electrode;

a gate insulating layer formed on the gate conductor;

a semiconductor layer formed on the gate insulating layer;

a data conductor including a drain electrode formed on at least a portion of the semiconductor layer;

an oxide film formed on the drain electrode, wherein coverage of the oxide film does not extend beyond the data conductor; and

a pixel electrode connected to the drain electrode.

11. The thin film array panel of claim 2 , wherein the oxide film comprises Molybdenum oxide.

12. A thin film array panel comprising:

a substrate;

a gate conductor formed on the substrate and including a gate electrode;

a gate insulating layer formed on the gate conductor;

a semiconductor layer formed on the gate insulating layer;

a data conductor including a source electrode and a drain electrode formed on at least a portion of the semiconductor layer;

an oxide film formed on the data conductor, wherein the oxide film comprises the same material as the data conductor as an oxide; and

a pixel electrode connected to the drain electrode.

13. The thin film array panel of claim 12 , wherein each of the oxide film and the data conductor comprises Mo.

14. The thin film array panel of claim 12 , wherein the data conductor comprises a first Mo containing metal film.

15. The thin film array panel of claim 14 , wherein the data conductor further comprises an Al containing metal film.

16. The thin film array panel of claim 15 , wherein the data conductor further comprises a second Mo containing metal film, and the Al containing metal film is interposed between the first and second Mo containing films.

17. The thin film array panel of claim 12 , wherein the oxide film has a thickness of about 10-20 Å.

18. The thin film array panel of claim 12 , further comprising a passivation layer disposed on the oxide film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029045/0860 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2004
From: KIM, SANG-GAB; KANG, SUNG-CHUL; KANG, HO-MIN; SONG, IN-HO; CHOE, HEE-HWAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 015526/0235 →