IP Library Granted Patent US 7,365,820
Granted Patent B2
US 7,365,820 · App. 10/878,535 · Granted Apr 29, 2008

In-plane switching mode liquid crystal display device and method of fabricating the same

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Quick Facts
Patent No.
US 7,365,820
App. No.
10/878,535
Granted
Apr 29, 2008
Kind
B2
Abstract

A liquid crystal display device includes first and second common electrode lines on a substrate extending along a first direction, a pair of adjacent data lines extending along a second direction perpendicular to the first direction to cross the first and second common electrode lines to define a unit pixel region, a gate line extending between the first and second common electrode lines along the first direction and crossing the pair of adjacent data lines, the first and second common electrode lines spaced apart from the gate line by a first distance along the second direction defining a first pixel region and a second pixel region of the unit pixel region, and a thin film transistor formed at the crossing of the gate line and one of the pair of adjacent data lines, the thin film transistor including a pair of drain electrodes, a source electrode, and a portion of the gate line, wherein each of the first and second pixel regions includes a circular pixel electrode and first and second circular common electrodes.

Claims (43)

1. An In-Plane Switching mode liquid crystal display device, comprising:

a unit pixel region bordered by first and second common electrode lines extending along a first direction, and bordered by a pair of adjacent data lines extending along a second direction perpendicular to the first direction;

a gate line extending through a middle region of the unit pixel region to define first and second pixel regions, the first and second common electrode lines spaced apart from the gate line by a first distance along the second direction, and the gate line crossing the pair of adjacent data lines at first and second edges of the middle region of the unit pixel region;

a thin film transistor formed at the first edge of the middle region of the unit pixel region, the thin film transistor including first and second drain electrodes, a source electrode, and a gate electrode;

first and second circular pixel electrodes, the first circular pixel electrode disposed within the first pixel region of the unit pixel region and electrically connected to the first drain electrode of the thin film transistor and the second circular pixel electrode disposed within the second pixel region of the unit pixel region and electrically connected to the second drain electrode of the thin film transistor;

first and second circular common electrodes connected to the first common line and disposed within the first pixel region, the first circular common electrode disposed at an interior center region of the first circular pixel electrode and the second circular common electrode disposed at an exterior lateral portion of the first circular pixel electrode; and

third and fourth circular common electrodes connected to the second common line and disposed within the second pixel region, the third circular common electrode disposed at an interior center region of the second circular pixel electrode and the fourth circular common electrode disposed at an exterior lateral portion of the second circular pixel electrode.

2. The device according to claim 1 , wherein the gate line functions as the gate electrode of the thin film transistor.

3. The device according to claim 2 , wherein the source electrode extends along the first direction overlying the gate line.

4. The device according to claim 1 , wherein the first circular pixel electrode and the first and second circular common electrodes are mutually concentric, and the second circular pixel electrode and the third and fourth circular common electrodes are mutually concentric.

5. The device according to claim 1 , wherein the first drain electrode includes a first portion that extends into the first pixel region and the second drain electrode includes a second portion that extends into the second pixel region.

6. The device according to claim 5 , wherein the first circular pixel electrode electrically contacts the first portion of the first drain electrode through a first contact hole, and the second circular pixel electrode electrically contacts the second portion of the second drain electrode through a second contact hole.

7. The device according to claim 1 , wherein the thin film transistor further comprises an active layer disposed between the source electrode and the gate electrode.

8. The device according to claim 7 , wherein a first conductive channel is formed within the active layer between the source electrode and the first drain electrode, and a second conductive channel is formed within the active layer between the source electrode and the second drain electrode.

9. The device according to claim 8 , wherein the thin film transistor further comprises an ohmic contact layer disposed between the active layer and the source electrode and the pair of drain electrodes.

10. The device according to claim 8 , wherein a centerline of the source electrode is coincident with centerlines of the active layer and the gate electrode.

11. The device according to claim 1 , wherein the first and second circular pixel electrodes are electrically connected to the thin film transistor through the first and second drain electrodes.

12. A method of fabricating an In-Plane Switching mode liquid crystal display device, comprising:

forming a gate line and first and second common electrode lines onto a substrate extending along a first direction, each of the common electrode lines having a vertical pattern extending along a second direction perpendicular to the first direction;

forming a gate insulating layer on the substrate including the gate line and the common electrode lines;

forming a source electrode, first and second drain electrodes and a data line on the substrate, the source electrode formed along the gate line, the data line crossing the gate line along a second direction perpendicular to the first direction to define a unit pixel region, the unit pixel region defined as first and second pixel regions by the gate line, a thin film transistor including a portion of the gate line, the source electrode, the first and second drain electrodes and formed along the gate line and at crossing region of the gate line and the data line;

forming a passivation layer on the substrate including the data line; and

forming a first circular pixel electrode and first and second circular common electrodes within the first pixel region and forming a second circular pixel electrode and third and fourth circular common electrodes Within the second pixel region, the first and second circular common electrodes formed at an interior and exterior regions of the first circular pixel electrode, and the third and fourth circular common electrodes formed at an interior and exterior regions of the second circular pixel electrode,

wherein the first circular pixel electrode is electrically connected to the first drain electrode of the thin film transistor, and the second circular pixel electrode is electrically connected to the second drain electrode of the thin film transistor.

13. The method according to claim 12 , wherein the first circular pixel electrode and the first and second circular common electrodes are mutually concentric, and the second circular pixel electrode and the third and fourth circular common electrodes are mutually concentric.

14. The method according to claim 12 , wherein forming the thin film transistor comprises:

sequentially depositing pure amorphous silicon and impurity-doped amorphous silicon onto the substrate including the gate insulating film; and

patterning the pure amorphous silicon and impurity-doped amorphous silicon to form an active layer and an ohmic contact layer, respectively.

15. The method according to claim 12 , wherein the first drain electrode includes a first portion that extends into the first pixel region and the second drain electrode includes a second portion that extends into the second pixel region.

16. The method according to claim 14 , wherein a first conductive channel is formed within the active layer between the source electrode and the first drain electrode, and a second conductive channel is formed within the active layer between the source electrode and the second drain electrode.

17. The method according to claim 16 , wherein a centerline of the source electrode is coincident with centerlines of the active layer and the gate line.

18. The method according to claim 12 , wherein the vertical pattern of the first common electrode line extends toward the gate line along the second direction into the first pixel region, and the vertical pattern of the second common electrode line extends toward the gate line along the second direction into the second pixel region.

19. The method according to claim 18 , wherein the first and second common electrodes electrically contact the vertical pattern of the first common electrode line via a first plurality of contact holes formed in the gate insulating film and the passivation layer, and the third and fourth common electrodes electrically contact the vertical pattern of the second common electrode line via a second plurality of holes formed in the gate insulating film and the passivation layer.

20. A liquid crystal display device, comprising:

first and second common electrode lines on a substrate extending along a first direction;

a pair of adjacent data lines extending along a second direction perpendicular to the first direction to cross the first and second common electrode lines to define a unit pixel region;

a gate line extending between the first and second common electrode lines along the first direction and crossing the pair of adjacent data lines, the first and second common electrode lines spaced apart from the gate line by a first distance along the second direction defining a first pixel region and a second pixel region of the unit pixel region; and

a thin film transistor formed at the crossing of the gate line and one of the pair of adjacent data lines, the thin film transistor including first and second drain electrodes, a source electrode, and a portion of the gate line,

wherein the first pixel region includes a first circular pixel electrode and first and second circular common electrodes each disposed at an interior and exterior regions of the first circular pixel electrode, and the second pixel region includes a second circular pixel electrode and third and fourth circular common electrodes each disposed at an interior and exterior regions of the second circular pixel electrode,

wherein the first circular pixel electrode is electrically connected to the first drain electrode of the thin film transistor, and the second circular pixel electrode is electrically connected to the second drain electrode of the thin film transistor.

21. The device according to claim 20 , wherein the gate line functions as the gate electrode of the thin film transistor.

22. The device according to claim 21 , wherein the source electrode extends along the first direction overlying the gate line.

23. The device according to claim 20 , wherein the first drain electrode includes a first portion that extends into the first pixel region and the second drain electrode includes a second portion that extends into the second pixel region.

Assignments (2)
CHANGE OF NAME Recorded Jun 19, 2008
From: LG.PHILIPS LCD CO., LTD.
To: LG DISPLAY CO., LTD.
Reel/Frame 021147/0009 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2004
From: CHAE, GEE SANG; LEE, YUN BOK
To: LG.PHILIPS LCD CO., LTD.
Reel/Frame 015525/0122 →