Dual access DRAM
View Patent ↗A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.
1. An dual access DRAM comprising:
a plurality of DRAM subarrays;
a plurality of sense amplifier columns for sensing data in the DRAM subarrays;
a first set of data lines;
a plurality of selection circuits respectively coupled between each sense amplifier column and the first set of data lines for selectively coupling the first set of data lines to the sense amplifier columns;
a second set of data lines; and
means for selectively coupling the second set of data lines to the sense amplifier columns,
wherein the first set of data lines is used for writing external data to a first DRAM subarray, or for providing external data read from a first DRAM subarray, and the second set of data lines is used to simultaneously transfer data between the first DRAM subarray and a second DRAM subarray; and
further comprising a data transfer register coupled between a first portion of the second set of data lines and a second portion of the second set of data lines to provide sufficient drive capability to correctly write the transferred data between the first DRAM subarray and the second DRAM.
2. The dual access DRAM of claim 1 wherein each selection circuit comprises:
a first transistor having a current path coupled between the sense amplifier column and a non-inverted data line, and a gate for receiving a selection control signal; and
a second transistor having a current path coupled between the sense amplifier column and an inverted data line, and a gate for receiving the selection control signal.
3. The dual access DRAM of claim 1 wherein each selection circuit comprises:
a first transistor having a current path coupled between a first plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a first selection control signal;
a second transistor having a current path coupled between the first plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the first selection control signal;
a third transistor having a current path coupled between a second plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a second selection control signal; and
a fourth transistor having a current path coupled between the second plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the second selection control signal.
4. The dual access DRAM of claim 1 wherein the means for selectively coupling the second set of data lines to the sense amplifier columns comprises a plurality of selection circuits respectively coupled between each sense amplifier column and the second set of data lines.
5. The dual access DRAM of claim 4 wherein each selection circuit comprises:
a first transistor having a current path coupled between the sense amplifier column and a non-inverted data line, and a gate for receiving a selection control signal; and
a second transistor having a current path coupled between the sense amplifier column and an inverted data line, and a gate for receiving the selection control signal.
6. The dual access DRAM of claim 4 wherein each selection circuit comprises:
a first transistor having a current path coupled between a first plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a first selection control signal;
a second transistor having a current path coupled between the first plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the first selection control signal;
a third transistor having a current path coupled between a second plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a second selection control signal; and
a fourth transistor having a current path coupled between the second plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the second selection control signal.
7. The dual access DRAM of claim 1 in which the second set of data lines is used to simultaneously transfer data between a second DRAM subarray and a third DRAM subarray.
8. An dual access DRAM comprising:
a plurality of DRAM subarrays;
a plurality of sense amplifier columns for sensing data in the DRAM subarrays;
a first set of data lines for reading and writing external data;
a plurality of selection circuits for respectively coupling the first set of data lines to the sense amplifier columns;
a second set of data lines for simultaneously transferring internal data; and
a plurality of selection circuits for respectively selectively coupling the second set of data lines to the sense amplifier columns,
wherein reading data from or writing data to a first DRAM subarray is performed via the first set of data lines and simultaneously transferring data from the first DRAM subarray to a second DRAM subarray is performed via a second set of data lines; and
further comprising a data transfer register coupled between a first portion of the second set of data lines and a second portion of the second set of data lines to provide sufficient drive capability to correctly write the transferred data between the first DRAM subarray and the second DRAM.
9. The dual access DRAM of claim 8 wherein each selection circuit for coupling the first set of data lines to the sense amplifier columns comprises:
a first transistor having a current path coupled between the sense amplifier column and a non-inverted data line, and a gate for receiving a selection control signal; and
a second transistor having a current path coupled between the sense amplifier column and an inverted data line, and a gate for receiving the selection control signal.
10. The dual access DRAM of claim 8 wherein each selection circuit for coupling the first set of data lines to the sense amplifier columns comprises:
a first transistor having a current path coupled between a first plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a first selection control signal;
a second transistor having a current path coupled between the first plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the first selection control signal;
a third transistor having a current path coupled between a second plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a second selection control signal; and
a fourth transistor having a current path coupled between the second plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the second selection control signal.
11. The dual access DRAM of claim 8 wherein each selection circuit for coupling the second set of data lines to the sense amplifier columns comprises:
a first transistor having a current path coupled between the sense amplifier column and a non-inverted data line, and a gate for receiving a selection control signal; and
a second transistor having a current path coupled between the sense amplifier column and an inverted data line, and a gate for receiving the selection control signal.
12. The dual access DRAM of claim 8 wherein each selection circuit for coupling the second set of data lines to the sense amplifier columns comprises:
a first transistor having a current path coupled between a first plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a first selection control signal;
a second transistor having a current path coupled between the first plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the first selection control signal;
a third transistor having a current path coupled between a second plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a second selection control signal; and
a fourth transistor having a current path coupled between the second plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the second selection control signal.
13. An dual access DRAM comprising:
a plurality of DRAM subarrays;
a plurality of sense amplifier columns for sensing data in the DRAM subarrays;
a first set of data lines;
means for selectively coupling the first set of data lines to the sense amplifier columns;
a second set of data lines; and
a plurality of selection circuits respectively coupled between each sense amplifier column and the second set of data lines for selectively coupling the second set of data lines to the sense amplifier columns,
wherein the first set of data lines is used for writing external data to a first DRAM subarray, or for providing external data read from a first DRAM subarray, and the second set of data lines is used to simultaneously transfer data between the first DRAM subarray and a second DRAM subarray; and
further comprising a data transfer register coupled between a first portion of the second set of data lines and a second portion of the second set of data lines to provide sufficient drive capability to correctly write the transferred data between the first DRAM subarray and the second DRAM.
14. The dual access DRAM of claim 13 wherein the means for selectively coupling the first set of data lines to the sense amplifier columns comprises a plurality of selection circuits respectively coupled between each sense amplifier column and the first set of data lines.
15. The dual access DRAM of claim 14 wherein each selection circuit comprises:
a first transistor having a current path coupled between the sense amplifier column and a non-inverted data line, and a gate for receiving a selection control signal; and
a second transistor having a current path coupled between the sense amplifier column and an inverted data line, and a gate for receiving the selection control signal.
16. The dual access DRAM of claim 14 wherein each selection circuit comprises:
a first transistor having a current path coupled between a first plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a first selection control signal;
a second transistor having a current path coupled between the first plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the first selection control signal;
a third transistor having a current path coupled between a second plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a second selection control signal; and
a fourth transistor having a current path coupled between the second plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the second selection control signal.
17. The dual access DRAM of claim 13 wherein each selection circuit comprises:
a first transistor having a current path coupled between the sense amplifier column and a non-inverted data line, and a gate for receiving a selection control signal; and
a second transistor having a current path coupled between the sense amplifier column and an inverted data line, and a gate for receiving the selection control signal.
18. The dual access DRAM of claim 13 wherein each selection circuit comprises:
a first transistor having a current path coupled between a first plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a first selection control signal;
a second transistor having a current path coupled between the first plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the first selection control signal;
a third transistor having a current path coupled between a second plurality of sense amplifiers in the sense amplifier column and a non-inverted data line, and a gate for receiving a second selection control signal; and
a fourth transistor having a current path coupled between the second plurality of sense amplifiers in the sense amplifier column and an inverted data line, and a gate for receiving the second selection control signal.
19. The dual access DRAM of claim 13 in which the second set of data lines is used to simultaneously transfer data between a second DRAM subarray and a third DRAM subarray.