Analog buffer and driving method thereof, liquid crystal display apparatus using the same and driving method thereof

1. An analog buffer for buffering an input voltage to an output line, comprising:

a constant current source to supply a constant current to the output line; and

a comparator to compare a voltage charged on the output line with the input voltage to turn-off the constant current source if it is determined that the voltage charged on the output line corresponding to the input voltage is buffered to the output line,

wherein the comparator includes:

an inverter connected between an input line of the input voltage and the constant current source;

a capacitor connected in series between the input line and the inverter;

a first switch to switch the input voltage on the input line;

a second switch connected between an input terminal and an output terminal of the inverter; and

a third switch connected between the input line and the output line,

wherein the constant current source includes:

a fourth switch to provide a conductive path between a first supply voltage line and the output line;

a fifth switch to control a conductive path between the fourth switch and the output line; and

a sixth switch connected in parallel to the output line,

wherein the first, second and sixth switches operate contrary to the third and fifth switches.

2. The analog buffer of claim 1 , further comprising a controller, connected between the comparator and the constant current source, to control a turn-on/turn-off of the constant current source in accordance with an output signal of the comparator.

3. The analog buffer of claim 2 , wherein the controller includes a second inverter to invert the output signal of the inverter to control the constant current source.

4. The analog buffer of claim 3 , further comprising a capacitor connected between an input terminal and an output terminal of the second inverter.

5. The analog buffer of claim 1 , wherein the sixth switch initializes the output line to a second supply voltage level.

6. The analog buffer of claim 5 , wherein the first, second, and sixth switches are turned-on, and the third and fifth switches are turned-off in accordance with a reset signal for a reset interval of the input voltage to initialize the comparator and the output line.

7. The analog buffer of claim 6 , wherein the first, second and sixth switches are turned-off, and the third and fifth switches are turned-on in accordance with the reset signal for a charging interval of the input voltage so that a voltage corresponding to the input voltage is charged to the output line.

8. The analog buffer of claim 7 , wherein each one of the first, second and third switches includes a first polarity transistor controlled by the reset signal and a second polarity transistor connected to the first polarity transistor in parallel and controlled by an inverted reset signal.

9. The analog buffer of claim 8 , wherein the sixth switch includes a first polarity transistor controlled by the inverted reset signal and a second polarity transistor connected to the first polarity transistor in parallel and controlled by the reset signal.

10. The analog buffer of claim 5 , further comprising:

a second capacitor connected in series with the feedback line;

a seventh switch connected between a node of the first switch and the capacitor and an input line of the second supply voltage; and

an eighth switch connected between the second capacitor and the input line of the second supply voltage.

11. The analog buffer of claim 10 , wherein the first, second, sixth and eighth switches are turned-on and the third, fifth and seventh switches are turned-off in accordance with a reset signal for a reset interval of the input voltage to initialize the comparator and the output line.

12. The analog buffer of claim 11 , wherein the first, second, sixth and the eighth switches are turned-off, and the third, fifth and seventh switches are turned-on in accordance with the reset signal for a charging interval of the input voltage so that a voltage corresponding to the input voltage is buffered to the output line.

13. The analog buffer of claim 12 , wherein a capacitance ratio of the capacitor and the second capacitor is modulated to adjust a voltage output through the output line.

14. The analog buffer of claim 1 , wherein each of the fourth and fifth switches includes a PMOS transistor.

15. The analog buffer of claim 14 , wherein the second supply voltage supplied to the sixth switch is a voltage lowered than a ground voltage or the input voltage, and a first supply voltage supplied to the fourth switch has a higher voltage level than the input voltage.

16. The analog buffer of claim 1 , wherein each of the fourth and fifth switches includes a NMOS transistor.

17. The analog buffer of claim 16 , wherein a voltage supplied to the fourth switch has a lower voltage level than the ground voltage or the input voltage, and a second supply voltage supplied has a higher voltage level than the input voltage.

18. A liquid crystal display apparatus using the analog buffer of claim 1 , comprising:

a data driver to drive data lines of a pixel matrix;

a gate driver to drive gate lines of the pixel matrix; and

a common voltage generator to supply a common voltage which is used as a reference voltage of the pixel matrix,

wherein any one of the data driver, the gate driver and the common voltage generator includes the analog buffer.