IP Library Granted Patent US 7,061,341
Granted Patent B1
US 7,061,341 · App. 10/879,715 · Granted Jun 13, 2006

System for highly linear phase modulation

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Quick Facts
Patent No.
US 7,061,341
App. No.
10/879,715
Granted
Jun 13, 2006
Kind
B1
Abstract

System for highly linear phase modulation. Apparatus is provided for linear phase modulation utilizing a phase-locked loop (PLL). The apparatus includes a PLL utilizing fractional N synthesis to realize a non-integer divide value. A two-port voltage-controlled oscillator includes a first port controlled by the phase-locked loop and a second port accessed for direct modulation. A second input to the fractional-N phase-locked loop is provided to remove the modulation introduced at the second port. Lastly, a calibration loop is provided wherein a frequency offset applied at the second port is adjusted until it cancels the effects of a known frequency offset introduced to the fractional-N phase-locked loop.

Claims (24)

1. A phase lock loop circuit that operates to produce a linear phase modulation signal, the phase lock loop circuit comprising:

oscillator means for producing a modulation signal based on a first oscillator control signal and a second oscillator control signal;

counter means for receiving the modulation signal and a counter control signal to produce a counter output signal that is used to derive the first oscillator control signal; and

calibration means for outputting the second oscillator control signal and the counter control signal, wherein the calibration means operates to adjust a frequency offset provided by the second oscillator control signal until canceling the effects of a frequency characteristic resulting from the counter control signal.

2. The phase lock loop circuit of claim 1 , wherein the calibration means comprises means for receiving phase data and producing a derivative of the phase data that is used to generate the second oscillator control signal and the counter control signal.

3. The phase lock loop circuit of claim 2 , wherein the calibration means comprises:

first modulator means for receiving the derivative of the phase data and producing a digital modulation signal;

digital-to-analog converter means for receiving the digital modulation signal and produce an analog modulation signal; and

filter means for receiving the analog modulation signal and producing the second oscillator control signal.

4. The phase lock loop circuit of claim 2 , wherein the calibration means comprises:

combining means for combining the derivative of the phase data and channel data to produce a combined modulation signal; and

second modulator means that operates to receive the combined modulation signal and produce the counter control signal.

5. A communication device comprising a phase lock loop circuit that operates to produce a linear phase modulation signal, the phase lock loop circuit comprising:

oscillator means for producing a modulation signal based on a first oscillator control signal and a second oscillator control signal;

counter means for receiving the modulation signal and a counter control signal to produce a counter output signal that is used to derive the first oscillator control signal; and

calibration means for outputting the second oscillator control signal and the counter control signal, wherein the calibration means operates to adjust a frequency offset provided by the second oscillator control signal until canceling the effects of a frequency characteristic resulting from the counter control signal.

6. The communication device of claim 5 , wherein the calibration means comprises means for receiving phase data and producing a derivative of the phase data that is used to generate the second oscillator control signal and the counter control signal.

7. The communication device of claim 6 , wherein the calibration means comprises:

first modulator means for receiving the derivative of the phase data and producing a digital modulation signal;

digital-to-analog converter means for receiving the digital modulation signal and produce an analog modulation signal; and

filter means for receiving the analog modulation signal and producing the second oscillator control signal.

8. The communication device of claim 6 , wherein the calibration means comprises:

combining means for combining the derivative of the phase data and channel data to produce a combined modulation signal; and

second modulator means that operates to receive the combined modulation signal and produce the counter control signal.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2017
From: GROE, JOHN
To: SEQUOIA COMMUNICATIONS CORP.
Reel/Frame 043643/0620 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2015
From: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
To: NXP B.V.
Reel/Frame 034854/0262 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2015
From: NXP B.V.
To: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
Reel/Frame 034752/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2015
From: NXP B.V.
To: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
Reel/Frame 034747/0893 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2014
From: QUINTIC HOLDINGS
To: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
Reel/Frame 034037/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2009
From: SEQUOIA COMMUNICATIONS CORPORATION
To: QUINTIC HOLDINGS
Reel/Frame 023639/0014 →