IP Library Granted Patent US 7,852,405
Granted Patent B1
US 7,852,405 · App. 10/879,961 · Granted Dec 14, 2010

Method and apparatus for high definition capture

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,852,405
App. No.
10/879,961
Granted
Dec 14, 2010
Kind
B1
Abstract

A method and apparatus for providing a high definition capture engine comprising an on-the-fly scaler to perform horizontal and vertical scaling as needed, prior to storage of the data in a buffer.

Claims (55)

1. A system for capturing a video data stream, the system comprising:

a plurality of signal buses operatively coupled together, including a video data bus and a memory interface bus;

a memory interface; and

a high definition capture (HDC) engine configured to:

capture high definition video data in real-time, the high definition video data having one of a plurality of formats;

capture a first region of interest (ROI) for video capture, specified as a sub-region in the video data stream using at least one of a vertical offset, a horizontal offset, a vertical size, and a horizontal size, the first ROI being smaller than an entire display screen;

capture a second ROI for data capture, specified as another sub-region in the video data stream that is non-overlapping with the first ROI for video capture using another vertical offset and another vertical size, and an indicator that indicates whether the second ROI includes a selected one of a horizontal blanking portion or an active video portion of the video data stream for capture as blanking data; and

perform video data format conversion within the captured first ROI using one of decimation or interpolation.

2. The system of claim 1 , wherein the HDC is further configured to extract synchronization information from the high definition video data, the synchronization information including different synchronization signal encoding types.

3. The system of claim 1 , wherein the HDC is further configured to convert a color space of the high definition video data.

4. The system of claim 1 , wherein the first ROI comprises any portion of an active video.

5. The system of claim 1 , wherein the first ROI is user defined.

6. The system of claim 1 , wherein video data format conversion comprises at least one of a 422 to 444 conversion or a 422 to 420 conversion.

7. A method of capturing a video data stream, the method comprising:

receiving a video data stream representing pixels, the video data stream having one of a plurality of formats and a plurality of components;

capturing a first region of interest (ROI) for video capture, specified as a sub-region in the video data stream;

capturing a second ROI for data capture, specified as another sub-region in the video data stream that is non-overlapping with the first ROI for video capture using a vertical offset and a vertical size, and an indicator that indicates whether the second ROI includes a selected one of a horizontal blanking portion or an active video portion of the video data stream for capture as blanking data; and

separating the plurality of components into a plurality of corresponding data streams;

performing a color space conversion on the plurality of corresponding data streams;

performing component delay equalization to synchronize the plurality of corresponding data streams;

generating control flags for vertical scaling;

performing horizontal down-scaling on the plurality of corresponding data streams;

changing pixel sampling rate from a pixel sampling clock rate to a global clock rate; and

performing horizontal up-scaling on the plurality of corresponding data streams.

8. The method of claim 7 , further comprising matching a rate of data sampling of the video data stream to a rate of a memory interface used for storing the video data stream in a computer memory.

9. The method of claim 7 , further comprising using command tokens to convey timing information about the video data stream to a memory interface used for storing the video data stream in a computer memory.

10. The method of claim 7 , further comprising an internal clock having a frequency higher than an external pixel clock associated with the video data stream, the internal clock being used for processing the video data stream if the external pixel clock is lost.

11. A device for capturing a video data stream, the device comprising:

an external video source interface for receiving a video data stream representing pixels, the video data stream having one of a plurality of formats and synchronization information including one of a plurality of synchronization signal encoding types;

a sync extraction module for extracting synchronization information from the video data stream;

a region of interest (ROI) module for defining a first ROI for video capture, the first ROI being specified as a sub-region in the video data stream using at least one of a vertical offset, a horizontal offset, a vertical size, and a horizontal size, and for defining a second ROI for data capture as another sub-region in the video data stream that is non-overlapping with the first ROI for video capture using another vertical offset and another vertical size, and an indicator that indicates whether the second ROI includes a selected one of a horizontal blanking portion or an active video portion of the video data stream for capture as blanking data;

a capture module for capturing the first ROI and the second ROI within the video data stream;

a component delay equalization module for synchronizing different pixel components within the captured first ROI;

a color conversion module for converting a color space of the video data stream within the captured first ROI; and

a scaler module for performing vertical and horizontal scaling of the video data stream within the captured first ROI.

12. The device of claim 11 , further comprising:

a high speed internal clock to acquire a pixel data clock associated with the video data stream; and

a FIFO buffer to resample the video data stream using an internally generated clock based on the high speed internal clock.

13. The device of claim 11 , further comprising a resampling logic to resample video data using an internally generated clock, such that no data is lost if an external clock signal is lost.

14. The device of claim 11 , wherein the synchronization signal encoding types include embedded synchronization, pulse based separate synchronization, and level based separate synchronization.

15. The device of claim 11 , further comprising a display processing unit.

16. A non-transitory unified memory having instructions encoded thereon that when executed perform actions comprising:

receiving a video data stream representing pixels, the video data stream having one of a plurality of formats and a plurality of components;

capturing a first region of interest (ROI) for video capture, specified as a sub-region in the video data stream;

capturing a second ROI for data capture, specified as another sub-region in the video data stream that is non-overlapping with the first ROI for video capture using a vertical offset and a vertical size, and an indicator that indicates whether the second ROI includes a selected one of a horizontal blanking portion or an active video portion of the video data stream for capture as blanking data;

separating the plurality of components into a plurality of corresponding data streams;

performing a color space conversion on the plurality of corresponding data streams;

performing component delay equalization to synchronize the plurality of corresponding data streams;

generating control flags for vertical scaling;

performing horizontal down-scaling on the plurality of corresponding data streams;

changing pixel sampling rate from a pixel sampling clock rate to a global clock rate; and

performing horizontal up-scaling on the plurality of corresponding data streams.

17. The unified memory of claim 16 , wherein the color space conversion comprises one of RGB to High Definition YUV, RGB to Standard Definition YUV, or High Definition YUV to Standard Definition YUV.

18. The unified memory of claim 16 , wherein the horizontal down-scaling is performed using the Fant algorithm.

19. The unified memory of claim 16 , wherein the vertical scaling is performed using vertical decimation.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2024
From: CSR TECHNOLOGY INC.
To: QUALCOMM INCORPORATED
Reel/Frame 069221/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2015
From: ZORAN CORPORATION
To: CSR TECHNOLOGY INC.
Reel/Frame 036642/0395 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: ZORAN CORPORATION
To: CSR TECHNOLOGY INC.
Reel/Frame 027550/0695 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2004
From: YEH, GERARD
To: ZORAN CORPORATION
Reel/Frame 015535/0583 →