Process for controlling the read amplifiers of a memory and corresponding memory integrated circuit

1. An integrated circuit comprising:

a memory comprising

a memory plane arranged in rows and columns,

a plurality of read amplifiers connected to the columns of said memory plane,

a reference path comprising first and second reference columns, and at least one reference memory cell connected between said first and second reference columns,

a reference row connected to said at least one reference memory cell for selection thereof so that said first reference column conducts a discharge current and said second reference column conducts a leakage current, and

a control circuit connected between said first and second reference columns and said plurality of read amplifiers, said control circuit providing an activation signal to said plurality of read amplifiers when an absolute value of a difference between voltages on said first and second reference columns exceeds a threshold.

2. An integrated circuit according to claim 1 , wherein said control circuit comprise an inverter controlled by the discharge and leakage currents from said first and second reference columns.

3. An integrated circuit according to claim 2 , wherein said control circuit further comprises a flip-flop having a first input connected to said first reference column, a second input connected to an output of said inverter, and an output for providing the activation signal.

4. An integrated circuit according to claim 1 , wherein said at least one reference memory cell is directly connected between said first and second reference columns.

5. An integrated circuit according to claim 4 , further comprising:

first and second reference path transistors respectively connected to said first and second reference columns; and

first and second global reference columns respectively connected to said first and second reference path transistors.

6. A memory comprising:

a memory plane arranged in rows and columns;

a plurality of read amplifiers connected to the columns of said memory plane;

a reference path comprising first and second reference columns, and at least one reference memory cell connected between said first and second reference columns;

a reference row connected to said at least one reference memory cell for selection thereof so that said first reference column conducts a discharge current and said second reference column conducts a leakage current; and

a control circuit connected between said first and second reference columns and said plurality of read amplifiers, said control circuit providing an activation signal to said plurality of read amplifiers based upon a difference between voltages on said first and second reference columns exceeding a threshold.

7. A memory according to claim 6 , wherein said control circuit comprise an inverter controlled by the discharge and leakage currents from said first and second reference columns.

8. A memory according to claim 7 , wherein said control circuit further comprises a flip-flop having a first input connected to said first reference column, a second input connected to an output of said inverter, and an output for providing the activation signal.

9. A memory according to claim 6 , wherein said at least one reference memory cell is directly connected between said first and second reference columns.

10. A memory according to claim 9 , further comprising:

first and second reference path transistors respectively connected to said first and second reference columns; and

first and second global reference columns respectively connected to said first and second reference path transistors.

11. A process for controlling a memory comprising a memory plane arranged in rows and columns, a plurality of read amplifiers connected to the columns of the memory plane, a reference path comprising first and second reference columns and at least one reference memory cell connected between the first and second reference columns, and a control circuit connected between the first and second reference columns and the plurality of read amplifiers, the process comprising:

selecting the at least one reference memory cell so that the first reference column conducts a discharge current and the second reference column conducts a leakage current; and

providing an activation signal from the control circuit to the plurality of read amplifiers when a difference between voltages on the first and second reference columns exceeds a threshold.

12. A process according to claim 11 , wherein the control circuit comprise an inverter controlled by the discharge and leakage currents from the first and second reference columns.

13. A process according to claim 12 , wherein the control circuit further comprises a flip-flop having a first input connected to the first reference column, a second input connected to an output of the inverter, and an output providing the activation signal.

14. A process according to claim 11 , wherein the at least one reference memory cell is directly connected between the first and second reference columns.

15. A process according to claim 14 , wherein the memory further comprises first and second reference path transistors respectively connected to the first and second reference columns; and first and second global reference columns respectively connected to the first and second reference path transistors.