Granted Patent B2

US 7,389,452 · App. 10/880,630 · Granted Jun 17, 2008

Abstract

Claims (42)

1. An integrated circuit comprising:

first and second circuit blocks each comprising a first internal node;

first and second multiplexer circuits each comprising first and second input nodes, a control node, and an output node, the first input node of the first multiplexer circuit coupled to the first internal node of the first circuit block, the first input node of the second multiplexer circuit coupled to the first internal node of the second circuit block, the second input nodes of the first and second multiplexer circuits coupled to logical 0, the control signal nodes of the first and second multiplexer circuits coupled to a control signal; and

an OR gate comprising a first input node coupled to the output node of the first multiplexer circuit, a second input node coupled to the output node of the second multiplexer circuit, and an output node;

wherein the control signal may be used to select the first internal node of the first circuit block or the first internal node of the second circuit block for monitoring at the output node of the OR gate.

2. The integrated circuit of claim 1 , wherein the first multiplexer circuit is located on an outside periphery of the first circuit block.

3. The integrated circuit of claim 1 , wherein the first multiplexer circuit is embedded within the first circuit block.

4. The integrated circuit of claim 1 , wherein the first multiplexer circuit is located on an outside periphery of the first circuit block, and the second multiplexer circuit is located on an outside periphery of the second circuit block.

5. The integrated circuit of claim 1 , wherein the first multiplexer circuit is embedded within the first circuit block, and the second multiplexer circuit is embedded within the second circuit block.

6. The integrated circuit of claim 1 , wherein the first input node of the first multiplexer circuit comprises a multi-bit input node.

7. The integrated circuit of claim 1 , wherein the first input node of the first multiplexer circuit comprises a single-bit input node.

8. The integrated circuit of claim 1 , wherein the control signal comprises a multi-bit signal.

9. The integrated circuit of claim 1 , wherein the control signal comprises an address.

10. The integrated circuit of claim 1 , further comprising an address bus coupled to the control nodes of the first and second multiplexer circuits.

11. The integrated circuit of claim 10 , further comprising a latch coupled between the address bus and the control nodes of the first and second multiplexer circuits.

12. The integrated circuit of claim 1 , wherein the output node of the OR gate comprises a first number of bits.

13. The integrated circuit of claim 12 , wherein the output node of the OR gate is coupled to a first number of external pins.

14. The integrated circuit of claim 12 , wherein the output node of the OR gate is coupled to a second number of external pins less than the first number of bits.

15. A method for debugging an integrated circuit, the method comprising:

providing first and second circuit blocks each comprising a first internal node;

providing first and second multiplexer circuits each comprising first and second input nodes, a control node, and an output node;

coupling the first input node of the first multiplexer circuit to the first internal node of the first circuit block;

coupling the first input node of the second multiplexer circuit to the first internal node of the second circuit block;

coupling the second input nodes of the first and second multiplexer circuits to logical 0;

coupling the control signal nodes of the first and second multiplexer circuits coupled to a control signal;

providing an OR gate comprising a first input node, a second input node and an output node;

coupling the first input node of the OR gate to the output node of the first multiplexer circuit;

coupling the second input node of the OR gate to the output node of the second multiplexer circuit; and

using the control signal to select the first internal node of the first circuit block or the first internal node of the second circuit block for monitoring at the output node of the OR gate.

16. The method of claim 15 , further comprising providing the first multiplexer circuit is located on an outside periphery of the first circuit block.

17. The method of claim 15 , further comprising embedding the first multiplexer circuit within the first circuit block.

18. The method of claim 15 , further comprising providing the first multiplexer circuit on an outside periphery of the first circuit block, and providing the second multiplexer circuit on an outside periphery of the second circuit block.

19. The method of claim 15 , further comprising embedding the first multiplexer circuit within the first circuit block, and embedding the second multiplexer circuit within the second circuit block.

20. The method of claim 15 , wherein the first input node of the first multiplexer circuit comprises a multi-bit input node.

21. The method of claim 15 , wherein the first input node of the first multiplexer circuit comprises a single-bit input node.

22. The method of claim 15 , wherein the control signal comprises a multi-bit signal.

23. The method of claim 15 , wherein the control signal comprises an address.

24. The method of claim 15 , further comprising providing an address bus coupled to the control nodes of the first and second multiplexer circuits.

25. The method of claim 24 , further comprising providing a latch coupled between the address bus and the control nodes of the first and second multiplexer circuits.

26. The method of claim 15 , wherein the output node of the OR gate comprises a first number of bits.

27. The method of claim 26 , wherein the output node of the OR gate is coupled to a first number of external pins.

28. The method of claim 26 , wherein the output node of the OR gate is coupled to a second number of external pins less than the first number of bits.

Assignments (12)