IP Library Granted Patent US 7,593,586
Granted Patent B2
US 7,593,586 · App. 10/882,038 · Granted Sep 22, 2009

Method and system for reducing artifacts in image detection

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Quick Facts
Patent No.
US 7,593,586
App. No.
10/882,038
Granted
Sep 22, 2009
Kind
B2
Abstract

An imager captures light reflecting off an object of interest and generates two or more images of the object. A controller identifies one or more non-interpretation regions in one of the captured images and uses the non-interpretation regions to reduce a number of artifacts in a final image.

Claims (29)

1. A method for reducing artifacts in a final image, by performing the following steps in sequential order:

a) generating by a processor, a first binary image that includes illuminated pixels that are artifacts captured by an imager and illuminated pixels that are part of an object of interest captured by the imager,

b) defining by the processor, one or more non-interpretation region in the first binary image, the non-interpretation region including the illuminated pixels that are artifacts and non-illuminated pixels that are in proximity to the illuminated pixels that are artifacts,

wherein the illuminated pixels that are part of the object of interest are excluded from the non-interpretation region,

c) generating by the processor, a second binary image by dilating the illuminated pixels that are artifacts of the non-interpretation region by illuminating the other non-illuminated pixels that are in proximity to the illuminated pixels that are artifacts,

wherein the second binary image excludes the illuminated pixels that are part of the object of interest,

d) inverting by the processor, the pixels of the second binary image, and

e) performing a logical AND by the processor of the pixels of the first binary image with the inverted pixels of the second binary image to de-illuminate the pixels that are artifacts while maintaining the illuminated pixels that are part of the object of interest,

wherein steps (a) through (e) are performed in sequential order.

2. The method of claim 1 , further comprising repeating:

generating a first binary image;

defining one or more non-interpretation regions in the first binary image; and

reducing a number of artifacts in a final image using the one or more non-interpretation regions;

a desired number of times.

3. The method of claim 1 , further comprising capturing images of an object.

4. The method of claim 3 , wherein the images of the object are captured sequentially.

5. The method of claim 4 , wherein generating a first binary image comprises generating a binary image of a first captured image.

6. The method of claim 5 , wherein a Boolean NAND operation is performed between the first binary image and the second binary image.

7. The method of claim 3 , wherein the images of the object comprise subframes.

8. The method of claim 7 , further comprising determining a difference between a first sub-frame image of the object and a second sub-frame image of the object to generate a difference image.

9. The method of claim 8 , wherein a binary image of the difference image is generated.

10. The method of claim 9 , wherein reducing a number of artifacts in a final image comprises:

generating a first sub-frame binary image of one of the sub-frame images;

performing a dilation operation on one of the sub-frame images to generate a second sub-frame binary image; and

performing a Boolean logic operation with the first sub-frame binary image and the second sub-frame binary image.

11. The method of claim 10 , wherein performing a Boolean logic operation with the first sub-frame binary image and the second sub-frame binary image comprises:

inverting the second sub-frame binary image; and

performing a Boolean AND operation with the first sub-frame binary image and the inverted second sub-frame binary image.

12. The method of claim 10 , wherein performing a Boolean logic operation with the first sub-frame binary image and the second sub-frame binary image comprises performing a Boolean NAND operation with the first sub-frame binary image and the second sub-frame binary image.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2009
From: MICRON TECHNOLOGY, INC.
To: APTINA IMAGING CORPORATION
Reel/Frame 022310/0331 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2008
From: AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.
To: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
Reel/Frame 021603/0690 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2007
From: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 019407/0441 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2007
From: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 018757/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.
Reel/Frame 017675/0691 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0738 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2004
From: HAVEN, RICHARD E.; VENKATESH, SHALINI
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 015499/0326 →