IP Library Granted Patent US 7,049,990
Granted Patent B2
US 7,049,990 · App. 10/882,427 · Granted May 23, 2006

Single loop feed-forward modulator with summing flash quantizer and multi-bit feedback

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Quick Facts
Patent No.
US 7,049,990
App. No.
10/882,427
Granted
May 23, 2006
Kind
B2
Abstract

A sigma-delta modulator includes a summing junction that receives an input signal. A plurality of integrators are arranged in series, the integrators output an integrated signal value to a multi-input quantizer. The multi-input quantizer has a plurality of comparators each with switched capacitor inputs. The multi-input quantizer outputs a quantized signal to a multi-bit feedback DAC that drives the summing junction.

Claims (45)

1. A sigma-delta modulator comprising:

a summing junction receiving an input signal;

a plurality of integrators in series, the integrators outputting an integrated signal value to a multi-input quantizer; and

wherein the multi-input quantizer has a plurality of comparators each with switched capacitor inputs, and

wherein the multi-input quantizer outputs a quantized signal to a multi-bit feedback DAC whose output drives the summing junction and, wherein each comparator implements a function Y=A 1 *S 1 +A 2 *S 2 +A 3 *S 3 +A 4 *S 4 +, . . . where Y is the output of the comparator, A 1 , A 2 , A 3 . . . are constants, and S 1 , S 2 , S 3 . . . are input voltages.

2. The sigma-delta modulator of claim 1 , wherein the sigma-delta modulator is a feed-forward modulator.

3. The sigma-delta modulator of claim 1 , wherein the quantized signal is a multi-level quantized signal.

4. The sigma-delta modulator of claim 1 , wherein each comparator of the plurality of comparators included in the multi-input quantizer comprises:

a first input and a second input, and an output;

a first plurality of capacitors connected to the first input acting as a summing junction, wherein each capacitor of the first plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage; and

a second plurality of capacitors connected to the second input acting as a summing junction, wherein each capacitor of the second plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage.

5. The sigma-delta modulator of claim 1 , wherein the multi-input quantizer outputs the quantized signal to a single multi-bit feedback DAC.

6. The sigma-delta modulator of claim 1 , wherein each comparator of the plurality of comparators included in the multi-input quantizer comprises:

a first plurality of inputs and a second plurality of inputs, and an output;

a first plurality of capacitors connected between the first plurality of inputs and a first summing junction, wherein each capacitor of the first plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage; and

a second plurality of capacitors connected between the second plurality of inputs and a second summing junction, wherein each capacitor of the second plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage.

7. A multi-input comparator comprising:

a first plurality of inputs and a second plurality of inputs, and an output;

a first plurality of capacitors connected between the first plurality of inputs and a first summing junction, wherein each capacitor of the first plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage; and

a second plurality of capacitors connected between the second plurality of inputs and a second summing junction, wherein each capacitor of the second plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage and, wherein the comparator implements a function Y=A 1 *S 1 +A 2 *S 2 +A 3 *S 3 +A 4 *S 4 + . . . , where Y is the output of the comparator, A 1 , A 2 , A 3 . . . are constants, and S 1 , S 2 , S 3 . . . are input voltages.

8. The comparator of claim 7 , wherein the comparator comprises a preamplifier connected to the first and second inputs, followed by a latch, such that the preamplifier includes a high gain amplifier.

9. The comparator of claim 7 , wherein the comparator is included in a multi-input quantizer, wherein the quantizer outputs a multi-level quantized signal.

10. A multi-input comparator comprising:

a first input and a second input, and an output;

a first plurality of capacitors connected to the first input, wherein each capacitor of the first plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage; and

a second plurality of capacitors connected to the second input, wherein each capacitor of the second plurality of capacitors is connected through a switch to one of a corresponding reference voltage and a corresponding input voltage,

wherein the comparator implements a function

Y=A 1 *S 1 +A 2 *S 2 +A 3 *S 3 +A 4 *S 4 + . . .

where Y is the output of the comparator, A 1 , A 2 , A 3 . . . are constants and S 1 , S 2 , S 3 . . . are the input voltages.

11. The comparator of claim 10 , wherein the comparator is included in a multi-input quantizer, wherein the quantizer outputs a multi-level quantized signal.

12. A sigma-delta modulator comprising:

a summing junction receiving an input signal;

a plurality of integrators in series, the integrators outputting an integrated signal value to a multi-input quantizer; and

wherein the multi-input quantizer has a plurality of comparators each with resistor inputs, and

wherein the multi-input quantizer outputs a quantized signal to a multi-bit feedback DAC whose output drives the summing junction and, wherein each comparator implements a function Y=A 1 *S 1 +A 2 *S 2 +A 3 *S 3 +A 4 *S 4 +, . . . where Y is the output of the comparator, A 1 , A 2 , A 3 . . . are constants, and S 1 , S 2 , S 3 . . . are input voltages.

13. The sigma-delta modulator of claim 12 , wherein the sigma-delta modulator is a feed-forward modulator.

14. The sigma-delta modulator of claim 12 , wherein the quantized signal is a multi-level quantized signal.

15. The sigma-delta modulator of claim 12 , wherein each comparator of the plurality of comparators included in the multi-input quantizer comprises:

a first input and a second input, and an output;

a first plurality of resistors connected to the first input acting as a summing junction, wherein each resistor of the first plurality of resistors is connected to one of a corresponding reference voltage and a corresponding input voltage; and

a second plurality of resistors connected to the second input acting as a summing junction, wherein each resistor of the second plurality of resistors is connected to one of a corresponding reference voltage and a corresponding input voltage.

16. The sigma-delta modulator of claim 12 , wherein each comparator of the plurality of comparators included in the multi-input quantizer comprises:

a first plurality of inputs and a second plurality of inputs, and an output;

a first plurality of resistors connected between the first plurality of inputs and a first summing junction, wherein each resistor of the first plurality of resistors is connected to one of a corresponding reference voltage and a corresponding input voltage; and

a second plurality of resistors connected between the second plurality of inputs and a second summing junction, wherein each resistor of the second plurality of resistors is connected to one of a corresponding reference voltage and a corresponding input voltage.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2004
From: RANGANATHAN, SUMANT
To: BROADCOM CORPORATION
Reel/Frame 015546/0387 →