Circuits and methods for synchronizing non-constant frequency switching regulators with a phase locked loop
View Patent ↗Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.
1. A method for synchronizing a non-constant frequency switching regulator that generates a regulated voltage output at an output node, the method comprising:
controlling the duty cycle of the switching regulator with control circuitry coupled to the output node and adapted to receive one or more variables, the control circuitry generating a pulse that is proportional or inversely proportional or approximately inversely proportional to one of the one or more variables;
providing as one of the one or more variables a signal corresponding to a voltage at an input node of the switching regulator or a signal corresponding to a voltage at the output node of the switching regulator; and
providing the control circuitry with an output of a phase locked loop having an input for receiving a clock signal and an output at which a signal is generated to control a parameter of the switching regulator, the phase locked loop adjusting the switching frequency of the switching regulator through control of the parameter.
2. The method of claim 1 , wherein the switching regulator comprises a synchronous switching regulator.
3. The method of claim 1 , wherein the switching regulator comprises a non-synchronous switching regulator.
4. The method of claim 1 , wherein the switching regulator comprises a hysteretic switching regulator and the hysteresis is adjusted by the phase locked loop.
5. The method of claim 1 , wherein the on-time of the switching regulator is adjusted by the phase locked loop.
6. The method of claim 1 , wherein the off-time of the switching regulator is adjusted by the phase locked loop.
7. The method of claim 1 , wherein the switching regulator comprises a switching regulator selected from the group consisting of: a step-down switching regulator; a step-up switching regulator; and a buck-boost switching regulator.
8. The method of claim 1 , wherein the switching regulator comprises a one shot timer to control the duty cycle of the switching regulator.
9. The method of claim 1 , wherein the phase locked loop comprises:
a first rising edge triggered data flip flop;
a second rising edge triggered data flip flop;
an AND gate coupled between the first and the second flip flops;
an amplifier coupled between the second flip flop and the one shot timer of the switching regulator; and
a loop filter to extract the DC average value from the second flip flop.
10. A method for synchronizing a plurality of non-constant frequency switching regulators, the method comprising:
providing a source voltage at a plurality of input nodes;
providing a regulated voltage at a plurality of output nodes;
providing control circuitry coupled to the plurality of output nodes to control the duty cycles of the plurality of regulators; and
providing a phase locked loop having an input for receiving a clock signal from a first switching regulator selected from the plurality of switching regulators and an output at which a signal is generated to control a parameter of a second switching regulator, the phase locked loop adjusting the switching frequency of the second switching regulator through control of the parameter.
11. The method of claim 10 , wherein the plurality of switching regulators comprises synchronous and non-synchronous switching regulators.
12. The method of claim 10 , wherein the plurality of switching regulators comprises one or more hysteretic switching regulators and the hysteresis is adjusted by the phase locked loop.
13. The method of claim 10 , wherein the plurality of switching regulators comprises one or more switching regulators, wherein their on-time is adjusted by the phase locked loop.
14. The method of claim 10 , wherein the plurality of switching regulators comprises one or more switching regulators, wherein their off-time is adjusted by the phase locked loop.
15. The method of claim 10 , wherein the plurality of switching regulators comprises one or more step-down switching regulators.
16. The method of claim 10 , wherein the plurality of switching regulators comprises one or more step-up switching regulators.
17. The method of claim 10 , wherein the plurality of switching regulators comprises one or more buck-boost switching regulators.
18. The method of claim 10 , further comprising controlling the duty cycle of each switching regulator from the plurality of switching regulators using one of: current-mode control, voltage-mode control, or a hybrid of current-mode and voltage-mode control.
19. The method of claim 10 , wherein each switching regulator from the plurality of switching regulators comprises a one shot timer to control the duty cycle of the switching regulator.
20. (currently amended) The method of claim 10 , wherein the phase locked loop comprises:
a first rising edge triggered data flip flop;
a second rising edge triggered data flip flop;
an AND gate coupled between the first and the second flip flops;
an amplifier coupled between the second flip flop and a one shot timer of the second switching regulator; and
a loop filter to extract the DC average value from the second flip flop.
21. The method of claim 20 , wherein the first flip flop comprises a clock input coupled to an output of a one shot timer of the first switching regulator.
22. The method of claim 20 , wherein the second flip flop comprises a clock input coupled to the output of the one shot timer of the first switching regulator.
23. A method for adjusting the switching frequency of a non-constant frequency switching regulator, the method comprising:
providing a one shot timer in the switching regulator to control the duty cycle of the switching regulator;
providing a phase locked loop connected to the one shot timer to control a parameter of the one shot timer, causing the switching frequency of the switching regulator to be adjusted through control of the parameter.
24. The method of claim 23 , wherein the phase locked loop comprises:
a first rising edge triggered data flip flop;
a second rising edge triggered data flip flop;
an AND gate coupled between the first and the second flip flops;
an amplifier coupled between the second flip flop and the one shot timer of the switching regulator; and
a loop filter to extract the DC average value from the second flip flop.
25. The method of claim 24 , wherein the first flip flop comprises a clock input coupled to a reference clock.
26. The method of claim 24 , wherein the second flip flop comprises a clock input coupled to the output of the one shot timer.
27. The method of claim 23 , wherein the switching regulator comprises a synchronous switching regulator.
28. The method of claim 23 , wherein the switching regulator comprises a non-synchronous switching regulator.
29. The method of claim 23 , wherein the on-time of the switching regulator is adjusted by the phase locked loop.
30. The method of claim 23 , wherein the off-time of the switching regulator is adjusted by the phase locked loop.
31. The method of claim 23 , wherein the switching regulator comprises a switching regulator selected from the group consisting of: a step-down switching regulator; a step-up switching regulator; and a buck-boost switching regulator.
32. The method of claim 23 , further comprising controlling the duty cycle of the switching regulator using one of: current-mode control, voltage-mode control, or a hybrid of current-mode and voltage-mode control.
33. A circuit for adjusting the switching frequency of a non-constant frequency switching regulator having a one shot timer to control the duty cycle of the switching regulator, the one shot timer coupled between an input voltage and a regulated output voltage, the circuit comprising:
a phase locked loop connected to the one shot timer to control a parameter of the one shot timer, causing the switching frequency of the switching regulator to be adjusted through control of the parameter.
34. The circuit of claim 33 , wherein the phase locked loop comprises:
a first rising edge triggered data flip flop;
a second rising edge triggered data flip flop;
an AND gate coupled between the first and the second flip flops;
an amplifier coupled between the second flip flop and the one shot timer; and
a loop filter to extract the DC average value from the second flip flop.
35. The circuit of claim 34 , wherein the first flip flop comprises a clock input coupled to a reference clock.
36. The circuit of claim 34 , wherein the second flip flop comprises a clock input coupled to the output of the one shot timer.
37. The circuit of claim 33 , wherein the switching regulator comprises a synchronous switching regulator.
38. The circuit of claim 33 , wherein the switching regulator comprises a non-synchronous switching regulator.
39. The circuit of claim 33 , wherein the on-time of the switching regulator is adjusted by the phase locked loop.
40. The circuit of claim 33 , wherein the off-time of the switching regulator is adjusted by the phase locked loop.
41. The circuit of claim 33 , wherein the switching regulator comprises a switching regulator selected from the group consisting of: a step-down switching regulator; a step-up switching regulator; and a buck-boost switching regulator.
42. The circuit of claim 33 , further comprising controlling the duty cycle of the switching regulator using one of: current-mode control, voltage-mode control, or a hybrid of current-mode and voltage-mode control.
43. A circuit for synchronizing a plurality of non-constant frequency switching regulators, each switching regulator from the plurality of switching regulators having a one shot timer to control the duty cycle of the switching regulator, the one shot timer coupled between an input voltage and a regulated output voltage, the circuit comprising:
a phase locked loop coupled between the one shot timer of a first switching regulator and the one shot timer of a second switching regulator selected from the plurality of switching regulators, the phase locked loop receiving a clock signal from the one shot timer of the first switching regulator and generating an output signal to control a parameter of the second switching regulator, the phase locked loop adjusting the switching frequency of the second switching regulator through control of the parameter.
44. The circuit of claim 43 , wherein the plurality of switching regulators comprises synchronous and non-synchronous switching regulators.
45. The circuit of claim 43 , wherein the plurality of switching regulators comprises one or more switching regulators, wherein their on-time is adjusted by the phase locked loop.
46. The circuit of claim 43 , wherein the plurality of switching regulators comprises one or more switching regulators, wherein their off-time is adjusted by the phase locked loop.
47. The circuit of claim 43 , wherein the plurality of switching regulators comprises one or more step-down switching regulators.
48. The circuit of claim 43 , wherein the plurality of switching regulators comprises one or more step-up switching regulators.
49. The method of claim 43 , wherein the plurality of switching regulators comprises one or more buck-boost switching regulators.
50. The circuit of claim 43 , further comprising controlling the duty cycle of each switching regulator from the plurality of switching regulators using one of: current-mode control, voltage-mode control, or a hybrid of current-mode and voltage-mode control.
51. The circuit of claim 43 , wherein each phase locked loop from the plurality of phase locked loops comprises:
a first rising edge triggered data flip flop;
a second rising edge triggered data flip flop;
an AND gate coupled between the first and the second flip flops;
an amplifier coupled between the second flip flop and the one shot timer of the second switching regulator; and
a loop filter to extract the DC average value from the second flip flop.
52. The circuit of claim 51 , wherein the first flip flop comprises a clock input coupled to the output of the one shot timer of the second switching regulator.
53. The circuit of claim 51 , wherein the second flip flop comprises a clock input coupled to the output of the one shot timer of the first switching regulator.