Thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
1. A thin film transistor array panel comprising:
a substrate;
a gate line formed on the substrate and including lower and upper films;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer;
a plurality of ohmic contacts formed on the semiconductor layer;
source and drain electrodes formed on the ohmic contacts and including lower and upper films;
a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and a portion of the gate insulating layer adjacent thereto and an opening exposing a first portion of the semiconductor layer;
a pixel electrode formed on the passivation layer and contacting the lower film of the drain electrode through the first contact hole; and
a columnar spacer formed on the exposed portion of the exposed first portion of the semiconductor layer.
2. The thin film transistor array panel of claim 1 , wherein the opening has at least an edge that coincides with an edge of the first portion of the semiconductor layer.
3. The thin film transistor array panel of claim 1 , wherein the upper film of the drain electrode has at least an edge that coincides with an edge of the first contact hole.
4. The thin film transistor array panel of claim 1 , wherein the lower film of the gate line has a first portion exposed out of the upper film of the gate line, the passivation layer further has a second contact hole exposing the first portion of the lower film of the gate line, and the first portion of the lower film of the gate line has an edge that coincide with an edge of the second contact hole.
5. The thin film transistor array panel of claim 4 , further comprising a contact assistant disposed on the first portion of the lower film of the gate line.
6. The thin film transistor array panel of claim 1 , wherein the upper film of the gate line and the upper conductive film comprises Cr and the lower film of the gate line and the lower conductive film comprises Al.
7. The thin film transistor array panel of claim 1 , further comprising a protection member disposed between and the spacer and the exposed first portion of the semiconductor layer.
8. A thin film transistor array panel comprising:
a substrate;
a plurality of gate lines formed on the substrate and including lower and upper films;
a gate insulating layer formed on the gate lines;
a semiconductor layer formed on the gate insulating layer;
a plurality of ohmic contacts formed on the semiconductor layer;
source and drain electrodes formed on the ohmic contacts and including lower and upper films;
a passivation layer formed on the source and the drain electrodes and having a plurality of first contact holes exposing portions of the drain electrodes and portions of the gate insulating layer adjacent thereto and a plurality of openings exposing first portions of the semiconductor layer;
a plurality of pixel electrodes formed on the passivation layer and contacting the lower films of the drain electrodes through the first contact holes; and
first and second columnar spacers formed on the exposed first portions of the semiconductor layer and having different heights.