Phase locked loop (PLL) frequency synthesizer and method
View Patent ↗A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.
1. A phase locked loop (PLL) circuit, comprising:
a primary phase locked loop circuit for establishing a reference signal;
a secondary phase locked loop circuit operatively connected to the primary phase locked loop circuit for receiving, isolating and outputting a reference signal to the primary phase locked loop circuit;
a board on which the primary and secondary phase locked loop circuits are positioned;
a plurality of isolation vias formed in the board that isolate circuit components of the primary and secondary phase locked loop circuits; and
a support member on which the board is mounted.
2. A phase locked loop (PLL) circuit according to claim 1 , and further comprising a filter within the secondary phase locked loop circuit for filtering the reference signal and attenuating spurs that are outside the secondary phase locked loop bandwidth.
3. A phase locked loop (PLL) circuit according to claim 1 , wherein said primary phase locked loop circuit comprises a voltage controlled oscillator (VCO) circuit and programmable divide circuit for establishing a voltage controlled oscillator signal and a reference signal at a divide ratio such that the signals are equal to a common phase comparison frequency.
4. A phase locked loop (PLL) circuit according to claim 3 , wherein said primary phase locked loop circuit further comprises a frequency multiplier circuit operatively connected to said voltage controlled oscillator for multiplying the frequency of the signal from the voltage controlled oscillator.
5. A phase locked loop (PLL) circuit according to claim 3 , and further comprising a processor operatively connected to said programmable divide circuit for establishing desired divide ratios between the voltage controlled oscillator and reference signals.
6. A phase locked loop (PLL) circuit according to claim 1 , wherein said secondary phase locked loop circuit includes an oscillator for generating a voltage controlled, clean reference signal, wherein said secondary phase locked loop circuit filters and synchronizes the clean reference signal with an external reference signal.
7. A phase locked loop (PLL) circuit according to claim 1 , wherein said board comprises a printed wiring board.
8. A phase locked loop (PLL) circuit according to claim 1 , wherein said support is substantially matched as to its coefficient of thermal expansion with the board.
9. A phase locked loop (PLL) circuit according to claim 1 , and further comprising a housing cover having an interior surface and channels on the interior surface that receive individual circuit components when the housing cover is mounted on the support.
10. A phase locked loop (PLL) circuit according to claim 3 , and further comprising channelization walls that are juxtaposed against any isolation vias used for isolating individual circuit components.
11. A method of generating a high frequency signal which comprises:
positioning circuit components of primary and secondary phase lock loop circuits on a board;
isolating the circuit components using isolation vias;
mounting the board on a support;
generating a reference signal with the primary phase locked loop circuit;
receiving and isolating a reference signal used for the primary phase locked loop circuit in a secondary phased locked loop circuit that is operatively connected to the primary phase locked loop circuit; and
generating from the secondary phase locked loop circuit a reference signal to the primary phase locked loop circuit.
12. A method according to claim 11 , which comprises filtering the external reference signal within the secondary phase locked loop circuit and attenuating any spurs that are outside the secondary phase locked loop circuit bandwidth.
13. A method according to claim 11 , which comprises establishing a voltage controlled oscillator signal and a reference signal at a divide ratio such that signals are equal to a common phase comparison frequency.
14. A method according to claim 13 , which comprises multiplying the frequency of the reference signal.
15. A method according to claim 13 , which comprises establishing divide ratios between the voltage controlled oscillator signal and the reference signal using a processor.
16. A method according to claim 11 , which comprises generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with an external reference signal for producing a reference signal to the primary phase locked loop circuit.
17. A method according to claim 11 , which comprises forming the board as a printed wiring board.
18. A method according to claim 11 , which comprises matching the coefficient of thermal expansion of the support with the board.
19. A method according to claim 11 , which comprises forming a housing cover having an interior surface and channels on the interior surface and receiving individual circuit components within the channels when the housing cover is mounted on the support.
20. A method according to claim 19 , which comprises forming channelization walls that are juxtaposed against isolation vias for isolating individual circuit components.