IP Library › Granted Patent US 6,987,696
Granted Patent B1
US 6,987,696 · App. 10/885,268 · Granted Jan 17, 2006

Method of improving erase voltage distribution for a flash memory array having dummy wordlines

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Quick Facts
Patent No.
US 6,987,696
App. No.
10/885,268
Granted
Jan 17, 2006
Kind
B1
Abstract

Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines.

Claims (17)

1. A method of erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines, comprising:

establishing an electrical connection between the dummy wordline and the end one of the operative wordlines; and

applying a gate erase voltage to the wordlines.

2. The method according to claim 1 , wherein the voltage of the dummy word line is approximately equal to the gate voltage.

3. The method according to claim 1 , wherein the electrical connection downwardly shifts an erase threshold voltage distribution for the end one of the operative wordlines.

4. The method according to claim 3 , wherein the voltage of the dummy word line and the shift in erase threshold voltage distribution have a generally linear relationship.

5. The method according to claim 3 , wherein the erase threshold voltage distribution for the end one of the operative wordlines is shifted to overlap with an erase threshold distribution for the operative wordlines disposed between the end operative wordlines.

6. The method according to claim 1 , wherein the memory devices are floating gate memory devices.

7. The method according to claim 6 , wherein the floating gate memory devices are erased using a Fowler-Nordheim (FN) erase.

8. The method according to claim 1 , wherein the memory devices are charge trapping dielectric memory devices having plural charge trapping regions.

9. The method according to claim 8 , wherein the charge trapping dielectric memory devices are erased using band-to-band (BTB) hot hole injection.

10. The method according to claim 8 , wherein a normal bit of each memory device and a complimentary bit of each memory device are erased in separate erase operations.

11. A flash memory unit configured for an erase operation, comprising:

a sector of memory devices defined by a plurality of operational wordlines and a plurality of bit lines;

at least one dummy wordline adjacent an end one of the operational wordlines; and

a logic unit electrically connecting the dummy wordline and the end one of the operational wordlines.

12. The flash memory unit according to claim 11 , wherein the memory devices are selected from one of floating gate memory devices and charge trapping dielectric memory devices.