Method of manufacturing electronic device and method of manufacturing semiconductor device
View Patent ↗The invention provides a semiconductor device, which removes troubles occurring when the parasitic capacitance between layered wiring lines with an interlayer insulating film therebetween is reduced, and have a simple structure and high reliability. The electronic device according to the invention can include a semiconductor layer formed on a substrate, a gate insulating layer formed on the semiconductor layer, a gate electrode having a predetermined pattern and formed on the gate insulating layer, an interlayer insulating film formed to cover the gate electrode, a source electrode and a drain electrode formed on the interlayer insulating film. The interlayer insulating film can be mainly made of silicon oxynitride with a nitrogen concentration of atomic percent or higher.
1. A method of manufacturing an electronic device, including a step of forming a layered structure, comprising the steps of:
forming a first conductive layer having a predetermined pattern above a base, the first conductive layer including a relatively low melting point conductive layer and first relatively high melting point conductive layer on the low melting point conductive layer;
forming an insulating layer mainly made of silicon oxynitride and having a nitrogen concentration of 2 atomic percent or higher on the first conductive layer;
forming a second conductive layer on the insulating layer; and
forming the insulating layer to be thicker than the first conductive layer during the insulating layer forming step.
2. The method of manufacturing an electronic device according to claim 1 , in addition to the layered structure forming step, the method further includes a step of annealing the formed layered structure.
3. The method of manufacturing an electronic device according to claim 2 , the annealing including heat-annealing based on heating.
4. The method of manufacturing an electronic device according to claim 2 , the annealing being performed in a water vapor atmosphere.
5. The method of manufacturing an electronic device according to claim 2 , the annealing lowering the nitrogen concentration of the insulating layer to 0.5 atomic percent or lower.
6. The method of manufacturing an electronic device according to claim 1 , the step of forming the first conductive layer further including the steps of:
forming a first relatively high melting point conductive layer on the base;
forming a relatively low melting point conductive layer on the first high melting point conductive layer; and
forming a second relatively high melting point conductive layer on the low melting point conductive layer, and
the second relatively high melting point conductive layer having a melting point higher than that of the low melting point conductive layer.
7. The method of manufacturing an electronic device according to claim 1 ,
the low melting point conductive layer including a layer mainly made of aluminum, and the second high melting point conductive layer being a layer mainly made of any one of high purity metal, metal nitride, and metal oxide.
8. The method of manufacturing an electronic device according to claim 1 ,
the insulating layer having a thickness of 800 nm and the first conductive layer having a thickness of 400 nm.
9. A method of manufacturing a semiconductor device including a step of forming a layered structure, comprising the steps of:
forming a semiconductor layer on a base;
forming a gate insulating layer on the semiconductor layer;
forming a gate electrode having a predetermined pattern on the gate insulating layer, the gate electrode including a relatively low melting point conductive layer and first relatively high melting point conductive layer on the low melting point conductive layer;
forming an interlayer insulating layer mainly made of silicon oxynitride and having a nitrogen concentration of 2 atomic percent or higher on the gate electrode;
forming a conductive layer on the interlayer insulating layer; and
forming the interlayer insulating layer to be thicker than the gate electrode.
10. The method of manufacturing a semiconductor device according to claim 9 ,
in addition to the step of forming the layered structure, the method further includes the step of annealing the layered structure.
11. The method of manufacturing a semiconductor device according to claim 9 ,
the interlayer insulating layer having a thickness of 800 nm and the gate electrode having a thickness of 400 nm.