IP Library Granted Patent US 7,447,261
Granted Patent B2
US 7,447,261 · App. 10/886,025 · Granted Nov 4, 2008

Adaptive frequency equalizer

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Quick Facts
Patent No.
US 7,447,261
App. No.
10/886,025
Granted
Nov 4, 2008
Kind
B2
Abstract

An adaptive frequency equalization system providing an equalizer that has programmable taps that adjusts magnitude and phase of symbol information of a received signal and that provides equalized symbol information. The system includes a hard decision circuit that selects ideal symbol values using the equalized symbol information. A frequency response circuit determines frequency response update values using the ideal symbol values and the received signal. An adjust circuit updates stored frequency response information using the frequency response update values, and also updates the programmable taps of the equalizer using the stored frequency response information.

Claims (54)

1. An adaptive frequency equalization system, comprising:

an equalizer with programmable taps configured to adjust magnitude and phase of symbol information of a received signal and to provide equalized symbol information;

a hard decision circuit configured to select ideal symbol values using said equalized symbol information;

a frequency response circuit configured to determine frequency response update values using said ideal symbol values and said received signal; and

an adjust circuit configured to update stored frequency response information using said frequency response update values during a transmitted frame, and to update said programmable taps of said equalizer using said stored frequency response information.

2. The adaptive frequency equalization system of claim 1 , wherein said adjust circuit comprises an inverter that inverts said stored frequency response information to provide tap coefficient values for said equalizer.

3. The adaptive frequency equalization system of claim 1 , further comprising:

a soft-decision circuit that determines soft decision symbols using said equalized symbol information and log likelihood ratio (LLR) weight factors; and

a power calculation circuit that generates said LLR weight factors from said stored frequency response information.

4. The adaptive frequency equalization system of claim 1 , wherein said frequency response circuit comprises:

a memory storing a set of update factors for each ideal symbol value, where each update factor is calculated by taking the absolute value of the square of the corresponding ideal symbol value, multiplying by a scale factor, and subtracting the result from one;

a first multiplier multiplying said stored frequency response information by a corresponding update factor from said memory;

a conjugate block for conjugating ideal symbol values from said hard decision circuit and that provides conjugated values;

a second multiplier multiplying symbol information from said received signal with a corresponding conjugated values from said conjugate block to provide corresponding frequency response estimate values;

a third multiplier multiplying each frequency response estimate value by said scale factor; and

an adder adding corresponding outputs from said first and third multipliers to determine said frequency response update values.

5. The adaptive frequency equalization system of claim 4 , wherein said memory comprises a lookup table.

6. The adaptive frequency equalization system of claim 1 , wherein said frequency response circuit determines said frequency response update values based on a least means squared (LMS) method, and wherein said adjust circuit stores inverted frequency response values used as coefficient values for said programmable taps of said equalizer.

7. An adaptive frequency equalization system, comprising:

an equalizer with programmable taps configured to adjust magnitude and phase of symbol information of a received signal and to provide equalized symbol information;

a hard decision circuit configured to select ideal symbol values using said equalized symbol information;

a frequency response circuit configured to determine frequency response update values using said ideal symbol values and said received signal;

an adjust circuit configured to update stored frequency response information using said frequency response update values during a transmitted frame, and to update said programmable taps of said equalizer using said stored frequency response information; and

a soft-decision circuit that determines soft decision symbols using said equalized symbol information and log likelihood ratio (LLR) weight factors, the soft-decision circuit being responsive to the frequency response update values; and

a power calculation circuit that generates said LLR weight factors from said stored frequency response information.

8. The adaptive frequency equalization system of claim 7 , wherein said adjust circuit comprises an inverter that inverts said stored frequency response information to provide tap coefficient values for said equalizer.

9. The adaptive frequency equalization system of claim 7 , wherein said frequency response circuit comprises:

a memory that stores a set of update factors for each ideal symbol value, where each update factor is calculated by taking the absolute value of the square of the corresponding ideal symbol value, multiplying by a scale factor, and subtracting the result from one.

10. The adaptive frequency equalization system of claim 9 , further comprising a first multiplier multiplying said stored frequency response information by a corresponding update factor from said memory.

11. The adaptive frequency equalization system of claim 10 , further comprising a conjugate block for conjugating ideal symbol values from said hard decision circuit and that provides conjugated values.

12. The adaptive frequency equalization system of claim 11 , further comprising a second multiplier multiplying symbol information from said received signal with a corresponding conjugated values from said conjugate block to provide corresponding frequency response estimate values.

13. The adaptive frequency equalization system of claim 9 , further comprising a third multiplier multiplying each frequency response estimate value by said scale factor.

14. The adaptive frequency equalization system of claim 9 , further comprising an adder adding corresponding outputs from said first and third multipliers to determine said frequency response update values.

15. An adaptive frequency equalization system, comprising:

means for adjusting magnitude and phase of symbol information of a received signal and providing equalized symbol information;

means for selecting ideal symbol values using said equalized symbol information;

means for determining frequency response update values using said ideal symbol values and said received signal;

means for updating stored frequency response information using said frequency response update values during a transmitted frame;

means for updating said programmable taps of said equalizer using said stored frequency response information;

means for determining soft decision symbols using said equalized symbol information;

means for logging likelihood ratio (LLR) weight factors; and

means for generating said LLR weight factors from said stored frequency response information.

16. The adaptive frequency equalization system of claim 15 , further comprising means for inverting said stored frequency response information to provide tap coefficient values for said equalizer.

17. The adaptive frequency equalization system of claim 15 , further comprising:

means for storing a set of update factors for each ideal symbol value, where each update factor is calculated by taking the absolute value of the square of the corresponding ideal symbol value, multiplying by a scale factor, and subtracting the result from one;

first means for multiplying said stored frequency response information by a corresponding update factor from said memory; and

means for conjugating ideal symbol values from said hard decision circuit and that provides conjugated values.

18. The adaptive frequency equalization system of claim 17 , further comprising:

second means for multiplying symbol information from said received signal with a corresponding conjugated values from said conjugate block to provide corresponding frequency response estimate values;

third means for multiplying each frequency response estimate value by said scale factor; and

means for adding corresponding outputs from said first means for multiplying and third means for multiplying to determine said frequency response update values.

19. The adaptive frequency equalization system of claim 18 , wherein said means for storing comprises a lookup table.

20. The adaptive frequency equalization system of claim 15 , further comprising means for determining said frequency response update values based on a least means squared (LMS) method; and

means for storing inverted frequency response values used as coefficient values for said programmable taps of said equalizer.

Assignments (5)
MERGER Recorded Jul 22, 2011
From: XOCYST TRANSFER AG L.L.C.
To: INTELLECTUAL VENTURES I LLC
Reel/Frame 026637/0603 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2009
From: CONEXANT SYSTEMS, INC.
To: XOCYST TRANSFER AG L.L.C.
Reel/Frame 022043/0607 →
RELEASE OF SECURITY INTEREST Recorded Oct 27, 2008
From: BANK OF NEW YORK MELLON TRUST COMPANY, N.A. (FORMERLY, BANK OF NEW YORK TRUST COMPANY, N.A.)
To: CONEXANT SYSTEMS INC.
Reel/Frame 021731/0807 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: CONEXANT SYSTEMS, INC.
To: THE BANK OF NEW YORK TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 018847/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2004
From: SHEARER, DANIEL D.; YEH, ALEX C.; WEBSTER, MARK A.; HALFORD, STEVEN D.
To: CONEXANT SYSTEMS, INC.
Reel/Frame 015990/0117 →