Method and system for an integrated host PCI I/O bridge and dual port gigabit Ethernet controller
View Patent ↗Aspects of the invention may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller.
1. A system providing an integrated networking interface, the system comprising:
a multiport Ethernet controller integrated within a single chip, said integrated multiport Ethernet controller comprising:
at least two gigabit Ethernet controllers, a common arbiter and a single PCI interface, wherein:
said at least two gigabit Ethernet controllers share said common arbiter;
said common arbiter is coupled to said single PCI interface; and
said common arbiter controls access to said single PCI interface by said at least two gigabit Ethernet controllers; and
an I/O bridge coupled to said single PCI interface of said integrated multiport Ethernet controller.
2. The system according to claim 1 , wherein said I/O bridge is coupled to an I/O function integrated within said single chip.
3. The system according to claim 2 , wherein said I/O function comprises an I/O logic and an I/O buffer, and said I/O function is coupled to at least one of said I/O bridge and said at least two gigabit Ethernet controllers.
4. The system according to claim 1 , wherein said I/O bridge is coupled to a host system.
5. The system according to claim 1 , comprises a timing function module integrated within said single chip, wherein said timing function module is coupled to at least one of said I/O bridge, said at least two gigabit Ethernet controllers and said I/O function.
6. The system according to claim 1 , wherein said I/O bridge comprises a primary bus controller.
7. The system according to claim 6 , wherein said primary bus controller is a primary PCI bus controller.
8. The system according to claim 6 , wherein said I/O bridge comprises a controller coupled to said primary bus controller.
9. The system according to claim 8 , wherein said controller comprises at least one control and status register.
10. The system according to claim 1 , wherein said I/O bridge comprises a secondary bus controller.
11. The system according to claim 10 , wherein said secondary bus controller is a secondary PCI bus controller.
12. The system according to claim 10 , wherein said I/O bridge comprises an I/O bridge interface coupled to said secondary bus controller.
13. The system according to claim 1 , wherein said I/O bridge comprises an inter-module bus interface coupled to at least one of a primary bus controller and a secondary bus controller.
14. A method providing an integrated networking interface, the method comprising:
in an I/O bridge integrated within a single chip:
controlling transfer of data across an inter-module bus interface integrated within said I/O bridge;
managing at least said inter-module bus interface via at least a first bus controller integrated within said I/O bridge; and
managing an Ethernet interface via at least a second bus controller, wherein:
said Ethernet interface and said at least a second bus controller are both integrated within said I/O bridge: and
said managing of at least said inter-module bus interface is performed, at least in part, concurrently with said managing of said Ethernet interface.
15. The method according to claim 14 , comprising managing at least another bus interface via said at least a first bus controller.
16. The method according to claim 1 , wherein said at least another bus interface is a PCI bus interface.
17. The method according to claim 14 , comprising independently processing at least a first Ethernet network connection and a second Ethernet network connection via said Ethernet interface.
18. The method according to claim 14 , wherein said at least said first bus controller integrated within said I/O bridge is a primary bus controller.
19. The method according to claim 18 , wherein said primary bus controller is a primary PCI bus controller.
20. The method according to claim 14 , wherein said at least said second bus controller integrated within said I/O bridge is a secondary bus controller.
21. The method according to claim 20 , wherein said secondary bus controller is a secondary PCI bus controller.
22. A method for communication, the method comprising:
in an integrated single chip comprises a multiport Ethernet controller and an I/O bridge, performing:
communicating data to a plurality of network connections via said multiport Ethernet controller, said multiport Ethernet controller comprising: at least two gigabit Ethernet controllers coupled to a single PCI interface via a shared common arbiter, wherein each of said at least two gigabit Ethernet controllers:
concurrently communicating data to a corresponding one of said plurality of network connections;
controlling access to said single PCI interface via said common arbiter, said common arbiter is coupled to said single PCI interface; and
controlling transfer of said communicated data from said single PCI interface to a host via said I/O bridge, wherein said I/O bridge is coupled to said single PCI interface of said multiport Ethernet controller.