Method and system for an integrated dual port gigabit ethernet controller chip

1. A method for processing network data, the method comprising:

receiving, by an integrated chip comprising first and second Ethernet controllers, a first request to access said first Ethernet controller from a first host process and a second request to access said first Ethernet controller from a second host process, the first and second host processes running on a host system external to the integrated chip;

arbitrating, by an arbiter of said integrated chip, which one of said first and second requests is granted access to said first Ethernet controller;

acknowledging, by said integrated chip, access to one of said first and second host processes based on said arbitrating; and

after transmitting said acknowledgment, facilitating, by said arbiter, transfer of data between said one of said first and second host processes running on the host system and a network via said first Ethernet controller.

2. The method according to claim 1 , comprising:

receiving, by said first Ethernet controller, first data from said network;

receiving, by said second Ethernet controller, second data from said network;

arbitrating which one of said first Ethernet controller and said second Ethernet controller can transfer data to a host process via a bus interface of said integrated chip; and

acknowledging a successful arbitration to one of said first Ethernet controller and said second Ethernet controller.

3. The method according to claim 2 , comprising:

if said first Ethernet controller receives an acknowledgement of successful arbitration, transferring said first data to said bus interface; and

if said second Ethernet controller receives an acknowledgement of successful arbitration, transferring said second data to said bus interface.

4. The method according to claim 3 , comprising:

tagging said first data received from said first Ethernet controller with a first unique identifier; and

tagging said second data received from said second Ethernet controller with a second unique identifier.

5. The method according to claim 1 , comprising receiving data from one of said first and second host processes via a bus interface of said integrated chip, said data comprising a combined ID and a unique function ID that identifies one of said first and second Ethernet controllers.

6. The method according to claim 5 , comprising determining which one of said first and second Ethernet controllers should receive said data for processing based on said combined and unique function IDs.

7. The method according to claim 6 , wherein said determining comprises determining whether said unique function ID comprises a first unique identifier identifying said data to be processed by said first Ethernet controller.

8. The method according to claim 6 , wherein said determining comprises determining whether said unique function ID comprises a second unique identifier identifying said data to be processed by said second Ethernet controller.

9. The method according to claim 5 , comprising transferring said data from said bus interface to at least one of said first Ethernet controller and said second Ethernet controller.

10. The method according to claim 1 , comprising arbitrating which one of said first Ethernet controller and said second Ethernet controller is permitted access to a shared resource of said integrated chip, said shared resource comprising at least one of shared boot code, a shared programming interface, and a semaphore memory access register.

11. A dual port Ethernet controller; comprising:

a bus interface;

a first Ethernet controller coupled to said bus interface;

a second Ethernet controller coupled to said bus interface, said bus interface, said first Ethernet controller, and said second Ethernet controller being integrated within a single chip; and

an arbiter configured to

receive, via said bus interface, a first request to access said first Ethernet controller from a first host process and a second request to access said first Ethernet controller from a second host process, the first and second host processes running on a host system external to the integrated chip,

arbitrate which one of said first and second requests is granted access to said first Ethernet controller, and

acknowledge access to one of said first and second host processes running on the host system based on said arbitrating.

12. The dual port Ethernet controller according to claim 11 , wherein said arbiter is coupled to said first Ethernet controller, said second Ethernet controller, and said bus interface.

13. The dual port Ethernet controller according to claim 12 , comprising:

a shared resource coupled to at least one of said first Ethernet controller, said second Ethernet controller, and said arbiter, wherein

said arbiter is further configured to arbitrate which one of said first Ethernet controller and said second Ethernet controller is permitted access to said shared resource.

14. The dual port Ethernet controller according to claim 13 , wherein said shared resource comprises at least one of a non-volatile memory that stores shared boot code, a shared general purpose input/out interface, and a semaphore memory access register.

15. The dual port Ethernet controller according to claim 14 , wherein said non-volatile memory comprises at least one of an EEPROM, a Flash memory, a 5 MBus interface and a serial programming interface.

16. The dual port Ethernet controller according to claim 14 , wherein said shared general purpose input/output interface comprises at least one general purpose pin.

17. The dual port Ethernet controller according to claim 12 , wherein at least one of said first Ethernet controller and said second Ethernet controller comprises:

an Ethernet transceiver;

a MAC controller coupled to said Ethernet transceiver;

a DMA controller coupled to at least one of said MAC controller and said arbiter;

a memory coupled to said MAC controller;

a transmit CPU coupled to at least one of said MAC controller and said memory;

a receive CPU coupled to at least one of said MAC controller and said memory; and

at least one control and status register coupled to at least one of said bus interface, said Ethernet transceiver, said MAC controller, said DMA controller, said memory, said transmit CPU, and said receive CPU.

18. The dual port Ethernet controller according to claim 17 , wherein said at least one control and status register comprises:

a bus interface register;

a status register; and

a control register.

19. The dual port Ethernet controller according to claim 17 , wherein said at least one control and status register comprises a MII interface register.

20. The dual port Ethernet controller according to claim 11 , wherein said bus interface is a PCI interface.

21. The dual port Ethernet controller according to claim 11 , comprising at least one of a clock generator and a phase lock loop integrated within said single chip and coupled to at least one of said bus interface, said first Ethernet controller, and said second Ethernet controller.

22. The dual port Ethernet controller according to claim 11 , comprising at least one LED interface integrated within said single chip and coupled to at least one of said bus interface, said first Ethernet controller, and said second Ethernet controller.

23. The dual port Ethernet controller according to claim 11 , comprising at least one debug interface integrated within said single chip and coupled to at least one of said bus interface, said first Ethernet controller, and said second Ethernet controller.

24. A dual port Ethernet controller comprising:

a bus interface;

a first Ethernet controller coupled to said bus interface;

a second Ethernet controller coupled to said bus interface, said bus interface, said first Ethernet controller, and said second Ethernet controller being integrated within a single chip;

an arbiter configured to

receive, via said bus interface, a first request to access said first Ethernet controller from a first host process and a second request to access said first Ethernet controller from a second host process,

arbitrate which one of said first and second requests is granted access to said first Ethernet controller, and

acknowledge access to one of said first and second host processes based on said arbitrating; and

at least one debug interface integrated within said single chip and coupled to at least one of said bus interface, said first Ethernet controller, and said second Ethernet controller,

wherein said at least one debug interface comprises a JTAG interface.